352 lines
8.8 KiB
C
352 lines
8.8 KiB
C
/* $NetBSD: cpu_subr.c,v 1.4 2001/11/19 23:30:07 matt Exp $ */
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/*-
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* Copyright (c) 2001 Matt Thomas.
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* Copyright (c) 2001 Tsubai Masanari.
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* Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by
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* Internet Research Institute, Inc.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_l2cr_config.h"
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#include "opt_multiprocessor.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <powerpc/mpc6xx/hid.h>
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#include <powerpc/spr.h>
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static void cpu_config_l2cr(int);
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int cpu;
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int ncpus;
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#ifdef MULTIPROCESSOR
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struct cpu_info cpu_info[CPU_MAXNUM];
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#else
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struct cpu_info cpu_info_store;
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#endif
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char cpu_model[80];
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struct cpu_info *
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cpu_attach_common(struct device *self, int id)
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{
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struct cpu_info *ci;
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u_int hid0, pvr, vers;
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char model[80];
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ncpus++;
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#ifdef MULTIPROCESSOR
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ci = &cpu_info[id];
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#else
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/*
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* If this isn't the primary CPU, print an error message
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* and just bail out.
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*/
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if (id != 0) {
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printf(": ID %d\n", id);
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printf("%s: processor off-line; multiprocessor support "
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"not present in kernel\n", self->dv_xname);
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return (NULL);
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}
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ci = &cpu_info_store;
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#endif
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ci->ci_cpuid = id;
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ci->ci_intrdepth = -1;
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ci->ci_dev = self;
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__asm __volatile ("mfpvr %0" : "=r"(pvr));
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vers = (pvr >> 16) & 0xffff;
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switch (id) {
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case 0:
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/* load my cpu_number to PIR */
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switch (vers) {
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case MPC604:
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case MPC604ev:
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case MPC7400:
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case MPC7410:
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case MPC7450:
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__asm __volatile ("mtspr %1,%0" :: "r"(id), "n"(SPR_PIR));
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}
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break;
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default:
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if (id >= CPU_MAXNUM) {
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printf(": more than %d cpus?\n", CPU_MAXNUM);
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panic("cpuattach");
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}
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#ifdef MULTIPROCESSOR
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printf(" not configured\n");
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return NULL;
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#endif
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}
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cpu_identify(model, sizeof(model));
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printf(": %s, ID %d%s\n", model, cpu_number(),
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id == 0 ? " (primary)" : "");
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__asm __volatile("mfspr %0,%1" : "=r"(hid0) : "n"(SPR_HID0));
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/*
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* Configure power-saving mode.
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*/
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switch (vers) {
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case MPC603:
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case MPC603e:
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case MPC603ev:
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case MPC604ev:
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case MPC750:
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case MPC7400:
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case MPC7410:
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/* Select DOZE mode. */
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_DOZE | HID0_DPM;
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powersave = 1;
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break;
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case MPC7450:
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/* Select NAP mode. */
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_NAP | HID0_DPM;
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powersave = 1;
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break;
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default:
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/* No power-saving mode is available. */
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}
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#ifdef NAPMODE
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switch (vers) {
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case MPC750:
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case MPC7400:
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/* Select NAP mode. */
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hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
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hid0 |= HID0_NAP;
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break;
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}
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#endif
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switch (vers) {
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case MPC750:
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hid0 &= ~HID0_DBP; /* XXX correct? */
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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break;
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case MPC7400:
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case MPC7410:
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hid0 &= ~HID0_SPD;
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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hid0 |= HID0_EIEC;
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break;
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}
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__asm __volatile ("mtspr %1,%0" :: "r"(hid0), "n"(SPR_HID0));
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#if 1
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{
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char hidbuf[128];
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bitmask_snprintf(hid0,
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vers == MPC7450 ? HID0_7450_BITMASK : HID0_BITMASK,
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hidbuf, sizeof hidbuf);
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printf("%s: HID0 %s\n", self->dv_xname, hidbuf);
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}
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#endif
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/*
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* Display cache configuration.
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*/
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if (vers == MPC750 || vers == MPC7400 ||
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vers == MPC7410 || vers == MPC7450) {
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printf("%s", self->dv_xname);
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cpu_config_l2cr(vers);
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}
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evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP,
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NULL, self->dv_xname, "traps");
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evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP,
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&ci->ci_ev_traps, self->dv_xname, "kernel DSI traps");
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evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP,
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&ci->ci_ev_traps, self->dv_xname, "user DSI traps");
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evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP,
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&ci->ci_ev_udsi, self->dv_xname, "user DSI failures");
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evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP,
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&ci->ci_ev_traps, self->dv_xname, "user ISI traps");
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evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP,
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&ci->ci_ev_isi, self->dv_xname, "user ISI failures");
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evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP,
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&ci->ci_ev_traps, self->dv_xname, "system call traps");
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evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP,
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&ci->ci_ev_traps, self->dv_xname, "PGM traps");
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evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP,
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&ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps");
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evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP,
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&ci->ci_ev_fpu, self->dv_xname, "FPU context switches");
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evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP,
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&ci->ci_ev_traps, self->dv_xname, "user alignment traps");
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evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP,
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&ci->ci_ev_ali, self->dv_xname, "user alignment traps");
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if (vers == MPC7400 || vers == MPC7410 || vers == MPC7450) {
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evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP,
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&ci->ci_ev_traps, self->dv_xname,
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"user AltiVec unavailable");
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evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP,
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&ci->ci_ev_vec, self->dv_xname,
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"user AltiVec context switches");
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}
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return ci;
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}
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struct cputab {
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int version;
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char *name;
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};
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static const struct cputab models[] = {
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{ MPC601, "601" },
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{ MPC602, "602" },
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{ MPC603, "603" },
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{ MPC603e, "603e" },
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{ MPC603ev, "603ev" },
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{ MPC604, "604" },
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{ MPC604ev, "604ev" },
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{ MPC620, "620" },
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{ MPC750, "750" },
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{ MPC7400, "7400" },
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{ MPC7410, "7410" },
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{ MPC7450, "7450" },
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{ MPC8240, "8240" },
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{ 0, NULL }
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};
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void
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cpu_identify(char *str, size_t len)
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{
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u_int pvr, vers, rev;
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const struct cputab *cp;
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asm ("mfpvr %0" : "=r"(pvr));
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vers = pvr >> 16;
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rev = pvr & 0xffff;
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for (cp = models; cp->name != NULL; cp++) {
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if (cp->version == vers)
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break;
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}
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if (str == NULL) {
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str = cpu_model;
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len = sizeof(cpu_model);
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cpu = vers;
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}
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if (cp->name != NULL) {
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snprintf(str, len, "%s (Revision %x)", cp->name, rev);
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} else {
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snprintf(str, len, "Version %x (Revision %x)", vers, rev);
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}
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}
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#ifdef L2CR_CONFIG
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u_int l2cr_config = L2CR_CONFIG;
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#else
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u_int l2cr_config = 0;
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#endif
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void
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cpu_config_l2cr(int vers)
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{
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u_int l2cr, x;
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__asm __volatile ("mfspr %0,%1" : "=r"(l2cr) : "n"(SPR_L2CR));
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/*
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* Configure L2 cache if not enabled.
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*/
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if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) {
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l2cr = l2cr_config;
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asm volatile ("mtspr %1,%0" :: "r"(l2cr), "n"(SPR_L2CR));
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/* Wait for L2 clock to be stable (640 L2 clocks). */
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delay(100);
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/* Invalidate all L2 contents. */
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l2cr |= L2CR_L2I;
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asm volatile ("mtspr %1,%0" :: "r"(l2cr), "n"(SPR_L2CR));
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do {
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asm volatile ("mfspr %0,%1" : "=r"(x) : "n"(SPR_L2CR));
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} while (x & L2CR_L2IP);
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/* Enable L2 cache. */
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l2cr &= ~L2CR_L2I;
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l2cr |= L2CR_L2E;
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asm volatile ("mtspr %1,%0" :: "r"(l2cr), "n"(SPR_L2CR));
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}
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if (l2cr & L2CR_L2E) {
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switch (l2cr & L2CR_L2SIZ) {
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case L2SIZ_256K:
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printf(": 256KB");
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break;
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case L2SIZ_512K:
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printf(": 512KB");
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break;
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case L2SIZ_1M:
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printf(": 1MB");
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break;
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default:
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printf(": unknown size");
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}
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#if 0
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switch (l2cr & L2CR_L2RAM) {
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case L2RAM_FLOWTHRU_BURST:
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printf(" Flow-through synchronous burst SRAM");
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break;
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case L2RAM_PIPELINE_BURST:
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printf(" Pipelined synchronous burst SRAM");
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break;
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case L2RAM_PIPELINE_LATE:
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printf(" Pipelined synchronous late-write SRAM");
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break;
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default:
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printf(" unknown type");
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}
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if (l2cr & L2CR_L2PE)
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printf(" with parity");
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#endif
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printf(" backside cache");
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} else
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printf(": L2 cache not enabled");
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printf("\n");
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}
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