481 lines
15 KiB
C
481 lines
15 KiB
C
/* $NetBSD: siop_common.c,v 1.2 2000/05/15 15:16:59 bouyer Exp $ */
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/*
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* Copyright (c) 2000 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* SYM53c7/8xx PCI-SCSI I/O Processors driver */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/buf.h>
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#include <sys/kernel.h>
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#include <sys/scsiio.h>
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#include <machine/endian.h>
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#include <machine/bus.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/vm_kern.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsi_message.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/ic/siopreg.h>
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#include <dev/ic/siopvar.h>
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#include <dev/ic/siopvar_common.h>
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#undef DEBUG
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#undef DEBUG_DR
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void
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siop_common_reset(sc)
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struct siop_softc *sc;
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{
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u_int32_t stest3;
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/* reset the chip */
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST);
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delay(1000);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0);
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/* init registers */
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0,
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SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 0);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0,
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0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL));
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1,
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0xff & ~(SIEN1_HTH | SIEN1_GEN));
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0,
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(0xb << STIME0_SEL_SHIFT));
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID,
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sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0,
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1 << sc->sc_link.scsipi_scsi.adapter_target);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
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(sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM);
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/* enable clock doubler or quadruler if appropriate */
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if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) {
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stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
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STEST1_DBLEN);
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if (sc->features & SF_CHIP_QUAD) {
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/* wait for PPL to lock */
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while ((bus_space_read_1(sc->sc_rt, sc->sc_rh,
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SIOP_STEST4) & STEST4_LOCK) == 0)
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delay(10);
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} else {
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/* data sheet says 20us - more won't hurt */
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delay(100);
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}
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/* halt scsi clock, select doubler/quad, restart clock */
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3,
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stest3 | STEST3_HSC);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
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STEST1_DBLEN | STEST1_DBLSEL);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3);
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} else {
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0);
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}
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if (sc->features & SF_CHIP_FIFO)
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5,
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bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) |
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CTEST5_DFS);
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sc->sc_reset(sc);
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}
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int
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siop_wdtr_neg(siop_cmd)
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struct siop_cmd *siop_cmd;
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{
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struct siop_softc *sc = siop_cmd->siop_target->siop_sc;
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struct siop_target *siop_target = siop_cmd->siop_target;
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int target = siop_cmd->xs->sc_link->scsipi_scsi.target;
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if (siop_target->status == TARST_WIDE_NEG) {
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/* we initiated wide negotiation */
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switch (siop_cmd->siop_table->msg_in[3]) {
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case MSG_EXT_WDTR_BUS_8_BIT:
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printf("%s: target %d using 8bit transfers\n",
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sc->sc_dev.dv_xname, target);
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siop_target->flags &= ~SF_BUS_WIDE;
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sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
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break;
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case MSG_EXT_WDTR_BUS_16_BIT:
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if (sc->features & SF_BUS_WIDE) {
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printf("%s: target %d using 16bit transfers\n",
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sc->sc_dev.dv_xname, target);
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siop_target->flags |= TARF_WIDE;
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sc->targets[target]->id |= (SCNTL3_EWS << 24);
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break;
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}
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/* FALLTHROUH */
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default:
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/*
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* hum, we got more than what we can handle, shoudn't
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* happen. Reject, and stay async
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*/
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siop_target->flags &= ~TARF_WIDE;
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siop_target->status = TARST_OK;
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printf("%s: rejecting invalid wide negotiation from "
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"target %d (%d)\n", sc->sc_dev.dv_xname, target,
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siop_cmd->siop_table->msg_in[3]);
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siop_cmd->siop_table->t_msgout.count= htole32(1);
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siop_cmd->siop_table->t_msgout.addr =
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htole32(siop_cmd->dsa);
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siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT;
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return SIOP_NEG_MSGOUT;
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}
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siop_cmd->siop_table->id =
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htole32(sc->targets[target]->id);
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bus_space_write_1(sc->sc_rt, sc->sc_rh,
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SIOP_SCNTL3,
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(sc->targets[target]->id >> 24) & 0xff);
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/* we now need to do sync */
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siop_target->status = TARST_SYNC_NEG;
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siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
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siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN;
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siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR;
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siop_cmd->siop_table->msg_out[3] = sc->minsync;
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siop_cmd->siop_table->msg_out[4] = sc->maxoff;
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siop_cmd->siop_table->t_msgout.count =
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htole32(MSG_EXT_SDTR_LEN + 2);
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siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa);
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return SIOP_NEG_MSGOUT;
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} else {
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/* target initiated wide negotiation */
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if (siop_cmd->siop_table->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT
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&& (sc->features & SF_BUS_WIDE)) {
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printf("%s: target %d using 16bit transfers\n",
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sc->sc_dev.dv_xname, target);
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siop_target->flags |= TARF_WIDE;
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sc->targets[target]->id |= SCNTL3_EWS << 24;
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siop_cmd->siop_table->msg_out[3] =
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MSG_EXT_WDTR_BUS_16_BIT;
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} else {
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printf("%s: target %d using 8bit transfers\n",
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sc->sc_dev.dv_xname, target);
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siop_target->flags &= ~SF_BUS_WIDE;
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sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
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siop_cmd->siop_table->msg_out[3] =
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MSG_EXT_WDTR_BUS_8_BIT;
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}
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siop_cmd->siop_table->id =
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htole32(sc->targets[target]->id);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
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(sc->targets[target]->id >> 24) & 0xff);
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/*
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* we did reset wide parameters, so fall back to async,
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* but don't shedule a sync neg, target should initiate it
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*/
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siop_target->status = TARST_OK;
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siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
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siop_cmd->siop_table->msg_out[1] = MSG_EXT_WDTR_LEN;
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siop_cmd->siop_table->msg_out[2] = MSG_EXT_WDTR;
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siop_cmd->siop_table->t_msgout.count=
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htole32(MSG_EXT_WDTR_LEN + 2);
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siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa);
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return SIOP_NEG_MSGOUT;
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}
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}
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int
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siop_sdtr_neg(siop_cmd)
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struct siop_cmd *siop_cmd;
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{
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struct siop_softc *sc = siop_cmd->siop_target->siop_sc;
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struct siop_target *siop_target = siop_cmd->siop_target;
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int target = siop_cmd->xs->sc_link->scsipi_scsi.target;
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int sync, offset, i;
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int send_msgout = 0;
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sync = siop_cmd->siop_table->msg_in[3];
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offset = siop_cmd->siop_table->msg_in[4];
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if (siop_target->status == TARST_SYNC_NEG) {
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/* we initiated sync negotiation */
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siop_target->status = TARST_OK;
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#ifdef DEBUG
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printf("sdtr: sync %d offset %d\n", sync, offset);
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#endif
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if (offset > sc->maxoff || sync < sc->minsync ||
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sync > sc->maxsync)
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goto reject;
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for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
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i++) {
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if (sc->clock_period != scf_period[i].clock)
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continue;
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if (scf_period[i].period == sync) {
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/* ok, found it. we now are sync. */
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printf("%s: target %d now synchronous at "
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"%sMhz, offset %d\n", sc->sc_dev.dv_xname,
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target, scf_period[i].rate, offset);
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sc->targets[target]->id &=
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~(SCNTL3_SCF_MASK << 24);
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sc->targets[target]->id |= scf_period[i].scf
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<< (24 + SCNTL3_SCF_SHIFT);
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if (sync < 25) /* Ultra */
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sc->targets[target]->id |=
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SCNTL3_ULTRA << 24;
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else
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sc->targets[target]->id &=
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~(SCNTL3_ULTRA << 24);
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sc->targets[target]->id &=
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~(SCXFER_MO_MASK << 8);
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sc->targets[target]->id |=
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(offset & SCXFER_MO_MASK) << 8;
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goto end;
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}
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}
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/*
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* we didn't find it in our table, do async and send reject
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* msg
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*/
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reject:
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send_msgout = 1;
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siop_cmd->siop_table->t_msgout.count= htole32(1);
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siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT;
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printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname,
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target);
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sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
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sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
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sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8);
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} else { /* target initiated sync neg */
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#ifdef DEBUG
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printf("sdtr (target): sync %d offset %d\n", sync, offset);
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#endif
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if (offset == 0 || sync > sc->maxsync) { /* async */
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goto async;
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}
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if (offset > sc->maxoff)
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offset = sc->maxoff;
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if (sync < sc->minsync)
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sync = sc->minsync;
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/* look for sync period */
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for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
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i++) {
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if (sc->clock_period != scf_period[i].clock)
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continue;
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if (scf_period[i].period == sync) {
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/* ok, found it. we now are sync. */
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printf("%s: target %d now synchronous at "
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"%sMhz, offset %d\n", sc->sc_dev.dv_xname,
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target, scf_period[i].rate, offset);
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sc->targets[target]->id &=
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~(SCNTL3_SCF_MASK << 24);
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sc->targets[target]->id |= scf_period[i].scf
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<< (24 + SCNTL3_SCF_SHIFT);
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if (sync < 25) /* Ultra */
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sc->targets[target]->id |=
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SCNTL3_ULTRA << 24;
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else
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sc->targets[target]->id &=
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~(SCNTL3_ULTRA << 24);
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sc->targets[target]->id &=
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~(SCXFER_MO_MASK << 8);
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sc->targets[target]->id |=
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(offset & SCXFER_MO_MASK) << 8;
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siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
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siop_cmd->siop_table->msg_out[1] =
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MSG_EXT_SDTR_LEN;
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siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR;
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siop_cmd->siop_table->msg_out[3] = sync;
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siop_cmd->siop_table->msg_out[4] = offset;
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siop_cmd->siop_table->t_msgout.count=
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htole32(MSG_EXT_SDTR_LEN + 2);
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send_msgout = 1;
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goto end;
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}
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}
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async:
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printf("%s: target %d asynchronous\n",
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sc->sc_dev.dv_xname, target);
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sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
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sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
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sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8);
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siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
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siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN;
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siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR;
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siop_cmd->siop_table->msg_out[3] = 0;
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siop_cmd->siop_table->msg_out[4] = 0;
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siop_cmd->siop_table->t_msgout.count=
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htole32(MSG_EXT_SDTR_LEN + 2);
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send_msgout = 1;
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}
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end:
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#ifdef DEBUG
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printf("id now 0x%x\n", sc->targets[target]->id);
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#endif
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siop_cmd->siop_table->id = htole32(sc->targets[target]->id);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
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(sc->targets[target]->id >> 24) & 0xff);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER,
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(sc->targets[target]->id >> 8) & 0xff);
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if (send_msgout) {
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siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa);
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return SIOP_NEG_MSGOUT;
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} else {
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return SIOP_NEG_ACK;
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}
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}
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void
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siop_minphys(bp)
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struct buf *bp;
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{
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minphys(bp);
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}
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int
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siop_ioctl(link, cmd, arg, flag, p)
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struct scsipi_link *link;
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u_long cmd;
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caddr_t arg;
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int flag;
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struct proc *p;
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{
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struct siop_softc *sc = link->adapter_softc;
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u_int8_t scntl1;
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int s;
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switch (cmd) {
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case SCBUSIORESET:
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s = splbio();
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scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1,
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scntl1 | SCNTL1_RST);
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/* minimum 25 us, more time won't hurt */
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delay(100);
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bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1);
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splx(s);
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return (0);
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default:
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return (ENOTTY);
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}
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}
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void
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siop_sdp(siop_cmd)
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struct siop_cmd *siop_cmd;
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{
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/* save data pointer. Handle async only for now */
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int offset, dbc, sstat;
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struct siop_softc *sc = siop_cmd->siop_target->siop_sc;
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scr_table_t *table; /* table to patch */
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if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN))
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== 0)
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|
return; /* no data pointers to save */
|
|
offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1);
|
|
if (offset >= SIOP_NSG) {
|
|
printf("%s: bad offset in siop_sdp (%d)\n",
|
|
sc->sc_dev.dv_xname, offset);
|
|
return;
|
|
}
|
|
table = &siop_cmd->siop_table->data[offset];
|
|
#ifdef DEBUG_DR
|
|
printf("sdp: offset %d count=%d addr=0x%x ", offset,
|
|
table->count, table->addr);
|
|
#endif
|
|
dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff;
|
|
if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) {
|
|
/* need to account stale data in FIFO */
|
|
int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO);
|
|
if (sc->features & SF_CHIP_FIFO) {
|
|
dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh,
|
|
SIOP_CTEST5) & CTEST5_BOMASK) << 8;
|
|
dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff;
|
|
} else {
|
|
dbc += (dfifo - (dbc & 0x7f)) & 0x7f;
|
|
}
|
|
sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0);
|
|
if (sstat & SSTAT0_OLF)
|
|
dbc++;
|
|
if (sstat & SSTAT0_ORF)
|
|
dbc++;
|
|
if (siop_cmd->siop_target->flags & TARF_WIDE) {
|
|
sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh,
|
|
SIOP_SSTAT2);
|
|
if (sstat & SSTAT2_OLF1)
|
|
dbc++;
|
|
if (sstat & SSTAT2_ORF1)
|
|
dbc++;
|
|
}
|
|
/* clear the FIFO */
|
|
bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
|
|
bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
|
|
CTEST3_CLF);
|
|
}
|
|
table->addr =
|
|
htole32(le32toh(table->addr) + le32toh(table->count) - dbc);
|
|
table->count = htole32(dbc);
|
|
#ifdef DEBUG_DR
|
|
printf("now count=%d addr=0x%x\n", table->count, table->addr);
|
|
#endif
|
|
}
|
|
|
|
void
|
|
siop_clearfifo(sc)
|
|
struct siop_softc *sc;
|
|
{
|
|
int timeout = 0;
|
|
int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3);
|
|
|
|
#ifdef DEBUG_INTR
|
|
printf("DMA fifo not empty !\n");
|
|
#endif
|
|
bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
|
|
ctest3 | CTEST3_CLF);
|
|
while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) &
|
|
CTEST3_CLF) != 0) {
|
|
delay(1);
|
|
if (++timeout > 1000) {
|
|
printf("clear fifo failed\n");
|
|
bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
|
|
bus_space_read_1(sc->sc_rt, sc->sc_rh,
|
|
SIOP_CTEST3) & ~CTEST3_CLF);
|
|
return;
|
|
}
|
|
}
|
|
}
|