533 lines
13 KiB
C
533 lines
13 KiB
C
/* $NetBSD: wstsc.c,v 1.8 1995/02/12 19:19:31 chopps Exp $ */
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/*
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* Copyright (c) 1994 Michael L. Hitch
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)supradma.c
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <scsi/scsi_all.h>
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#include <scsi/scsiconf.h>
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#include <amiga/amiga/device.h>
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#include <amiga/amiga/isr.h>
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#include <amiga/dev/scireg.h>
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#include <amiga/dev/scivar.h>
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#include <amiga/dev/zbusvar.h>
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int wstscprint __P((void *auxp, char *));
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void wstscattach __P((struct device *, struct device *, void *));
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int wstscmatch __P((struct device *, struct cfdata *, void *));
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int wstsc_dma_xfer_in __P((struct sci_softc *dev, int len,
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register u_char *buf, int phase));
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int wstsc_dma_xfer_out __P((struct sci_softc *dev, int len,
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register u_char *buf, int phase));
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int wstsc_dma_xfer_in2 __P((struct sci_softc *dev, int len,
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register u_short *buf, int phase));
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int wstsc_dma_xfer_out2 __P((struct sci_softc *dev, int len,
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register u_short *buf, int phase));
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int wstsc_intr __P((struct sci_softc *));
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struct scsi_adapter wstsc_scsiswitch = {
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sci_scsicmd,
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sci_minphys,
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0, /* no lun support */
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0, /* no lun support */
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};
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struct scsi_device wstsc_scsidev = {
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NULL, /* use default error handler */
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NULL, /* do not have a start functio */
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NULL, /* have no async handler */
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NULL, /* Use default done routine */
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};
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#define QPRINTF
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#ifdef DEBUG
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extern int sci_debug;
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#endif
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extern int sci_data_wait;
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int supradma_pseudo = 0; /* 0=none, 1=byte, 2=word */
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struct cfdriver wstsccd = {
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NULL, "wstsc", (cfmatch_t)wstscmatch, wstscattach,
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DV_DULL, sizeof(struct sci_softc), NULL, 0 };
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/*
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* if this a Supra WordSync board
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*/
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int
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wstscmatch(pdp, cdp, auxp)
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struct device *pdp;
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struct cfdata *cdp;
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void *auxp;
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{
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struct zbus_args *zap;
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zap = auxp;
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/*
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* Check manufacturer and product id.
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*/
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if (zap->manid == 1056 && zap->prodid == 12) /* add other boards? */
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return(1);
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else
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return(0);
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}
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void
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wstscattach(pdp, dp, auxp)
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struct device *pdp, *dp;
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void *auxp;
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{
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volatile u_char *rp;
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struct sci_softc *sc;
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struct zbus_args *zap;
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printf("\n");
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zap = auxp;
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sc = (struct sci_softc *)dp;
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rp = zap->va;
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/*
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* set up 5380 register pointers
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* (Needs check on which Supra board this is - for now,
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* just do the WordSync)
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*/
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sc->sci_data = rp + 0;
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sc->sci_odata = rp + 0;
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sc->sci_icmd = rp + 2;
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sc->sci_mode = rp + 4;
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sc->sci_tcmd = rp + 6;
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sc->sci_bus_csr = rp + 8;
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sc->sci_sel_enb = rp + 8;
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sc->sci_csr = rp + 10;
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sc->sci_dma_send = rp + 10;
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sc->sci_idata = rp + 12;
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sc->sci_trecv = rp + 12;
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sc->sci_iack = rp + 14;
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sc->sci_irecv = rp + 14;
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if (supradma_pseudo == 2) {
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sc->dma_xfer_in = wstsc_dma_xfer_in2;
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sc->dma_xfer_out = wstsc_dma_xfer_out2;
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}
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else if (supradma_pseudo == 1) {
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sc->dma_xfer_in = wstsc_dma_xfer_in;
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sc->dma_xfer_out = wstsc_dma_xfer_out;
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}
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sc->sc_isr.isr_intr = wstsc_intr;
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sc->sc_isr.isr_arg = sc;
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sc->sc_isr.isr_ipl = 2;
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add_isr(&sc->sc_isr);
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scireset(sc);
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sc->sc_link.adapter_softc = sc;
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sc->sc_link.adapter_target = 7;
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sc->sc_link.adapter = &wstsc_scsiswitch;
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sc->sc_link.device = &wstsc_scsidev;
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sc->sc_link.openings = 1;
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TAILQ_INIT(&sc->sc_xslist);
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/*
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* attach all scsi units on us
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*/
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config_found(dp, &sc->sc_link, wstscprint);
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}
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/*
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* print diag if pnp is NULL else just extra
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*/
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int
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wstscprint(auxp, pnp)
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void *auxp;
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char *pnp;
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{
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if (pnp == NULL)
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return(UNCONF);
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return(QUIET);
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}
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int
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wstsc_dma_xfer_in (dev, len, buf, phase)
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struct sci_softc *dev;
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int len;
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register u_char *buf;
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int phase;
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{
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int wait = sci_data_wait;
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u_char csr;
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u_char *obp = (u_char *) buf;
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volatile register u_char *sci_dma = dev->sci_idata;
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volatile register u_char *sci_csr = dev->sci_csr;
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QPRINTF(("supradma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
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*dev->sci_tcmd = phase;
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*dev->sci_icmd = 0;
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*dev->sci_mode = SCI_MODE_DMA;
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*dev->sci_irecv = 0;
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while (len >= 128) {
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wait = sci_data_wait;
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while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
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(SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
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if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
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|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
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|| --wait < 0) {
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#ifdef DEBUG
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if (sci_debug | 1)
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printf("supradma2_in fail: l%d i%x w%d\n",
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len, *dev->sci_bus_csr, wait);
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#endif
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*dev->sci_mode = 0;
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return 0;
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}
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}
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#define R1 (*buf++ = *sci_dma)
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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R1; R1; R1; R1; R1; R1; R1; R1;
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len -= 128;
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}
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while (len > 0) {
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wait = sci_data_wait;
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while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
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(SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
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if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
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|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
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|| --wait < 0) {
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#ifdef DEBUG
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if (sci_debug | 1)
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printf("supradma1_in fail: l%d i%x w%d\n",
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len, *dev->sci_bus_csr, wait);
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#endif
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*dev->sci_mode = 0;
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return 0;
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}
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}
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*buf++ = *sci_dma;
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len--;
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}
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QPRINTF(("supradma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
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len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
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obp[6], obp[7], obp[8], obp[9]));
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*dev->sci_mode = 0;
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return 0;
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}
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int
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wstsc_dma_xfer_out (dev, len, buf, phase)
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struct sci_softc *dev;
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int len;
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register u_char *buf;
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int phase;
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{
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int wait = sci_data_wait;
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u_char csr;
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u_char *obp = buf;
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volatile register u_char *sci_dma = dev->sci_data;
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volatile register u_char *sci_csr = dev->sci_csr;
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QPRINTF(("supradma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
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QPRINTF(("supradma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
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len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
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buf[6], buf[7], buf[8], buf[9]));
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*dev->sci_tcmd = phase;
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*dev->sci_mode = SCI_MODE_DMA;
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*dev->sci_icmd = SCI_ICMD_DATA;
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*dev->sci_dma_send = 0;
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while (len > 0) {
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wait = sci_data_wait;
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while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
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(SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
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if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
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|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
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|| --wait < 0) {
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#ifdef DEBUG
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if (sci_debug)
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printf("supradma_out fail: l%d i%x w%d\n",
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len, csr, wait);
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#endif
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*dev->sci_mode = 0;
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return 0;
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}
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}
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*sci_dma = *buf++;
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len--;
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}
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wait = sci_data_wait;
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while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
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SCI_CSR_PHASE_MATCH && --wait);
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*dev->sci_mode = 0;
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*dev->sci_icmd = 0;
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return 0;
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}
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int
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wstsc_dma_xfer_in2 (dev, len, buf, phase)
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struct sci_softc *dev;
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int len;
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register u_short *buf;
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int phase;
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{
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int wait = sci_data_wait;
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u_char csr;
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u_char *obp = (u_char *) buf;
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volatile register u_short *sci_dma = (u_short *)(dev->sci_idata + 0x10);
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volatile register u_char *sci_csr = dev->sci_csr + 0x10;
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QPRINTF(("supradma_in2 %d, csr=%02x\n", len, *dev->sci_bus_csr));
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*dev->sci_tcmd = phase;
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*dev->sci_mode = SCI_MODE_DMA;
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*dev->sci_icmd = 0;
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*(dev->sci_irecv + 16) = 0;
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while (len >= 128) {
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#if 0
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wait = sci_data_wait;
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while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
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(SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
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if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
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|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
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|| --wait < 0) {
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#ifdef DEBUG
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if (sci_debug | 1)
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printf("supradma2_in2 fail: l%d i%x w%d\n",
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len, *dev->sci_bus_csr, wait);
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#endif
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*dev->sci_mode &= ~SCI_MODE_DMA;
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return 0;
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}
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}
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#else
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while (!(*sci_csr & SCI_CSR_DREQ))
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;
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#endif
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#define R2 (*buf++ = *sci_dma)
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R2; R2; R2; R2; R2; R2; R2; R2;
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R2; R2; R2; R2; R2; R2; R2; R2;
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R2; R2; R2; R2; R2; R2; R2; R2;
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R2; R2; R2; R2; R2; R2; R2; R2;
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R2; R2; R2; R2; R2; R2; R2; R2;
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R2; R2; R2; R2; R2; R2; R2; R2;
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R2; R2; R2; R2; R2; R2; R2; R2;
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R2; R2; R2; R2; R2; R2; R2; R2;
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len -= 128;
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}
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while (len > 0) {
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#if 0
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wait = sci_data_wait;
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while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
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(SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
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if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
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|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
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|| --wait < 0) {
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#ifdef DEBUG
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if (sci_debug | 1)
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printf("supradma1_in2 fail: l%d i%x w%d\n",
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len, *dev->sci_bus_csr, wait);
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#endif
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*dev->sci_mode &= ~SCI_MODE_DMA;
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return 0;
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}
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}
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#else
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while (!(*sci_csr * SCI_CSR_DREQ))
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;
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#endif
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*buf++ = *sci_dma;
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len -= 2;
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}
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QPRINTF(("supradma_in2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
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len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
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obp[6], obp[7], obp[8], obp[9]));
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*dev->sci_irecv = 0;
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*dev->sci_mode = 0;
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return 0;
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}
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int
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wstsc_dma_xfer_out2 (dev, len, buf, phase)
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struct sci_softc *dev;
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int len;
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register u_short *buf;
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int phase;
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{
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int wait = sci_data_wait;
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u_char csr;
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u_char *obp = (u_char *) buf;
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volatile register u_short *sci_dma = (ushort *)(dev->sci_data + 0x10);
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volatile register u_char *sci_bus_csr = dev->sci_bus_csr;
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QPRINTF(("supradma_out2 %d, csr=%02x\n", len, *dev->sci_bus_csr));
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QPRINTF(("supradma_out2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
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len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
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obp[6], obp[7], obp[8], obp[9]));
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*dev->sci_tcmd = phase;
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*dev->sci_mode = SCI_MODE_DMA;
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*dev->sci_icmd = SCI_ICMD_DATA;
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*dev->sci_dma_send = 0;
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while (len > 64) {
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#if 0
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wait = sci_data_wait;
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while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
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(SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
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if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
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|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
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|| --wait < 0) {
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#ifdef DEBUG
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if (sci_debug)
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printf("supradma_out2 fail: l%d i%x w%d\n",
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len, csr, wait);
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#endif
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*dev->sci_mode = 0;
|
|
return 0;
|
|
}
|
|
}
|
|
#else
|
|
*dev->sci_mode = 0;
|
|
*dev->sci_icmd &= ~SCI_ICMD_ACK;
|
|
while (!(*sci_bus_csr & SCI_BUS_REQ))
|
|
;
|
|
*dev->sci_mode = SCI_MODE_DMA;
|
|
*dev->sci_dma_send = 0;
|
|
#endif
|
|
|
|
#define W2 (*sci_dma = *buf++)
|
|
W2; W2; W2; W2; W2; W2; W2; W2;
|
|
W2; W2; W2; W2; W2; W2; W2; W2;
|
|
if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ)
|
|
;
|
|
len -= 64;
|
|
}
|
|
|
|
while (len > 0) {
|
|
#if 0
|
|
wait = sci_data_wait;
|
|
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
|
|
(SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
|
|
if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
|
|
|| !(*dev->sci_bus_csr & SCI_BUS_BSY)
|
|
|| --wait < 0) {
|
|
#ifdef DEBUG
|
|
if (sci_debug)
|
|
printf("supradma_out2 fail: l%d i%x w%d\n",
|
|
len, csr, wait);
|
|
#endif
|
|
*dev->sci_mode = 0;
|
|
return 0;
|
|
}
|
|
}
|
|
#else
|
|
*dev->sci_mode = 0;
|
|
*dev->sci_icmd &= ~SCI_ICMD_ACK;
|
|
while (!(*sci_bus_csr & SCI_BUS_REQ))
|
|
;
|
|
*dev->sci_mode = SCI_MODE_DMA;
|
|
*dev->sci_dma_send = 0;
|
|
#endif
|
|
|
|
*sci_dma = *buf++;
|
|
if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ)
|
|
;
|
|
len -= 2;
|
|
}
|
|
|
|
#if 0
|
|
wait = sci_data_wait;
|
|
while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
|
|
SCI_CSR_PHASE_MATCH && --wait);
|
|
#endif
|
|
|
|
|
|
*dev->sci_irecv = 0;
|
|
*dev->sci_icmd &= ~SCI_ICMD_ACK;
|
|
*dev->sci_mode = 0;
|
|
*dev->sci_icmd = 0;
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
wstsc_intr(dev)
|
|
struct sci_softc *dev;
|
|
{
|
|
int i, found;
|
|
u_char stat;
|
|
|
|
if ((*(dev->sci_csr + 0x10) & SCI_CSR_INT) == 0)
|
|
return (0);
|
|
stat = *(dev->sci_iack + 0x10);
|
|
return (1);
|
|
}
|