95 lines
3.3 KiB
C
95 lines
3.3 KiB
C
/* $NetBSD: aicavar.h,v 1.1 2003/08/24 17:33:29 marcus Exp $ */
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/*
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* Copyright (c) 2003 SHIMIZU Ryo <ryo@misakimix.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _AICAVAR_H_
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#define _AICAVAR_H_
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typedef struct {
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u_int32_t serial;
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u_int32_t command;
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u_int32_t blocksize;
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u_int32_t channel;
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u_int32_t rate;
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u_int32_t precision;
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u_int32_t l_param; /* volume,etc... for left */
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u_int32_t r_param; /* volume,etc... for right */
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} aica_cmd_t;
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#define AICA_COMMAND_NOP 0
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#define AICA_COMMAND_PLAY 1
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#define AICA_COMMAND_STOP 2
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#define AICA_COMMAND_INIT 3
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#define AICA_COMMAND_MVOL 4
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#define AICA_COMMAND_VOL 5
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#define AICA_ARM_CODE 0x00000000 /* text+data+bss+stack
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0x00000000-0x0000ff00 */
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#define AICA_ARM_CMD 0x0000ff00 /* SH4<->ARM work for
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communication */
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#define AICA_ARM_CMDADDR(x) (AICA_ARM_CMD + offsetof(aica_cmd_t, x))
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#define AICA_ARM_CMD_SERIAL AICA_ARM_CMDADDR(serial)
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#define AICA_ARM_CMD_COMMAND AICA_ARM_CMDADDR(command)
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#define AICA_ARM_CMD_BLOCKSIZE AICA_ARM_CMDADDR(blocksize)
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#define AICA_ARM_CMD_CHANNEL AICA_ARM_CMDADDR(channel)
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#define AICA_ARM_CMD_RATE AICA_ARM_CMDADDR(rate)
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#define AICA_ARM_CMD_PRECISION AICA_ARM_CMDADDR(precision)
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#define AICA_ARM_CMD_LPARAM AICA_ARM_CMDADDR(l_param)
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#define AICA_ARM_CMD_RPARAM AICA_ARM_CMDADDR(r_param)
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#define AICA_ARM_END 0x00010000
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#define AICA_DMABUF_START 0x00010000
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#define AICA_DMABUF_LEFT 0x00010000 /* DMA buffer for PLAY
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0x00010000-0x0001FFFF */
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#define AICA_DMABUF_RIGHT 0x00020000 /* DMA buffer for PLAY
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0x00020000-0x0002FFFF */
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#define AICA_DMABUF_MONO AICA_DMABUF_LEFT
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#define AICA_DMABUF_END 0x00030000
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#define AICA_DMABUF_SIZE 0x0000ffc0
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#define AICA_MEMORY_END 0x00200000
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#define L256TO16(l) (((l) >> 4) & 0x0f)
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#define L16TO256(l) ((((l) << 4) & 0xf0) + ((l) & 0x0f))
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enum MIXER_CLASS {
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AICA_MASTER_VOL = 0,
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AICA_OUTPUT_GAIN,
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AICA_OUTPUT_CLASS,
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AICA_NDEVS
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};
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#endif /* _AICAVAR_H_ */
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