254 lines
8.5 KiB
C
254 lines
8.5 KiB
C
/* $NetBSD: tx39sibreg.h,v 1.2 2000/03/03 19:54:37 uch Exp $ */
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/*
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* Copyright (c) 2000, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Toshiba TX3912 SIB module
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*/
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#define TX39_SIBSIZE_REG 0x060 /* W */
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#define TX39_SIBSNDRXSTART_REG 0x064 /* W */
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#define TX39_SIBSNDTXSTART_REG 0x068 /* W */
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#define TX39_SIBTELRXSTART_REG 0x06c /* W */
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#define TX39_SIBTELTXSTART_REG 0x070 /* W */
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#define TX39_SIBCTRL_REG 0x074 /* R/W */
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#define TX39_SIBSNDHOLD_REG 0x078 /* R/W */
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#define TX39_SIBTELHOLD_REG 0x07c /* R/W */
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#define TX39_SIBSF0CTRL_REG 0x080 /* R/W */
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#define TX39_SIBSF1CTRL_REG 0x084 /* R/W */
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#define TX39_SIBSF0STAT_REG 0x088 /* R */
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#define TX39_SIBSF1STAT_REG 0x08c /* R */
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#define TX39_SIBDMACTRL_REG 0x090 /* R/W */
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/*
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* SIB DMA
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*/
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#define TX39_SIBDMA_SIZE 16384
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/*
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* SIB Size Register
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*/
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#define TX39_SIBSIZE_SND_SHIFT 18
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#define TX39_SIBSIZE_TEL_SHIFT 2
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#define TX39_SIBSIZE_MASK 0xfff
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#define TX39_SIBSIZE_SNDSIZE_SET(cr, val) \
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((cr) | (((((val) >> 2) - 1) << TX39_SIBSIZE_SND_SHIFT) & \
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(TX39_SIBSIZE_MASK << TX39_SIBSIZE_SND_SHIFT)))
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#define TX39_SIBSIZE_TELSIZE_SET(cr, val) \
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((cr) | (((((val) >> 2) - 1) << TX39_SIBSIZE_TEL_SHIFT) & \
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(TX39_SIBSIZE_MASK << TX39_SIBSIZE_TEL_SHIFT)))
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/*
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* SIB Sound RX Start Register
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* [1:0] reserved
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*/
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/*
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* SIB Sound TX Start Register
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* [1:0] reserved
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*/
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/*
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* SIB Telecom RX Start Register
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* [1:0] reserved
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*/
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/*
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* SIB Telecom TX Start Register
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* [1:0] reserved
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*/
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/*
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* SIB Control Register
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*/
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#define TX39_SIBCTRL_SIBIRQ 0x80000000
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#define TX39_SIBCTRL_ENCNTTEST 0x40000000 /* Don't set */
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#define TX39_SIBCTRL_ENDMATEST 0x20000000 /* Don't set */
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#define TX39_SIBCTRL_SNDMONO 0x10000000
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#define TX39_SIBCTRL_RMONOSNDIN 0x08000000
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#define TX39_SIBCTRL_SCLKDIV_SHIFT 24
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#define TX39_SIBCTRL_SCLKDIV_MASK 0x7
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#define TX39_SIBCTRL_SCLKDIV(cr) \
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(((cr) >> TX39_SIBCTRL_SCLKDIV_SHIFT) & \
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TX39_SIBCTRL_SCLKDIV_MASK)
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#define TX39_SIBCTRL_SCLKDIV_SET(cr, val) \
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((cr) | (((val) << TX39_SIBCTRL_SCLKDIV_SHIFT) & \
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(TX39_SIBCTRL_SCLKDIV_MASK << TX39_SIBCTRL_SCLKDIV_SHIFT)))
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#define TX39_SIBCTRL_TEL16 0x00800000
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#define TX39_SIBCTRL_TELFSDIV_SHIFT 16
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#define TX39_SIBCTRL_TELFSDIV_MASK 0x7f
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#define TX39_SIBCTRL_TELFSDIV(cr) \
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(((cr) >> TX39_SIBCTRL_TELFSDIV_SHIFT) & \
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TX39_SIBCTRL_TELFSDIV_MASK)
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#define TX39_SIBCTRL_TELFSDIV_SET(cr, val) \
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((cr) | (((val) << TX39_SIBCTRL_TELFSDIV_SHIFT) & \
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(TX39_SIBCTRL_TELFSDIV_MASK << TX39_SIBCTRL_TELFSDIV_SHIFT)))
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#define TX39_SIBCTRL_SND16 0x00008000
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#define TX39_SIBCTRL_SNDFSDIV_SHIFT 8
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#define TX39_SIBCTRL_SNDFSDIV_MASK 0x7f
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#define TX39_SIBCTRL_SNDFSDIV(cr) \
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(((cr) >> TX39_SIBCTRL_SNDFSDIV_SHIFT) & \
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TX39_SIBCTRL_SNDFSDIV_MASK)
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#define TX39_SIBCTRL_SNDFSDIV_SET(cr, val) \
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((cr) | (((val) << TX39_SIBCTRL_SNDFSDIV_SHIFT) & \
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(TX39_SIBCTRL_SNDFSDIV_MASK << TX39_SIBCTRL_SNDFSDIV_SHIFT)))
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#define TX39_SIBCTRL_SELTELSF1 0x00000080
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#define TX39_SIBCTRL_SELSNDSF1 0x00000040
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#define TX39_SIBCTRL_ENTEL 0x00000020
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#define TX39_SIBCTRL_ENSND 0x00000010
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#define TX39_SIBCTRL_SIBLOOP 0x00000008
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#define TX39_SIBCTRL_ENSF1 0x00000004
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#define TX39_SIBCTRL_ENSF0 0x00000002
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#define TX39_SIBCTRL_ENSIB 0x00000001
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/*
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* SIB Sound RX/TX Holding Register
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*/
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/*
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* SIB Telecom RX/TX Holding Register
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*/
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/*
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* SIB Subframe 0 Control Register
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* SIB Subframe 0 Status Register
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*/
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/* Control/Status bit, field definition (See also UCB1200) */
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#define TX39_SIBSF0_REGADDR_SHIFT 27
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#define TX39_SIBSF0_REGADDR_MASK 0xf
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#define TX39_SIBSF0_REGADDR(cr) \
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(((cr) >> TX39_SIBSF0_REGADDR_SHIFT) & \
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TX39_SIBSF0_REGADDR_MASK)
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#define TX39_SIBSF0_REGADDR_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF0_REGADDR_SHIFT) & \
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(TX39_SIBSF0_REGADDR_MASK << TX39_SIBSF0_REGADDR_SHIFT)))
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#define TX39_SIBSF0_WRITE 0x04000000
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#define TX39_SIBSF0_SNDVALID 0x00020000
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#define TX39_SIBSF0_TELVALID 0x00010000
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#define TX39_SIBSF0_REGDATA_SHIFT 0
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#define TX39_SIBSF0_REGDATA_MASK 0xffff
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#define TX39_SIBSF0_REGDATA(cr) \
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(((cr) >> TX39_SIBSF0_REGDATA_SHIFT) & \
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TX39_SIBSF0_REGDATA_MASK)
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#define TX39_SIBSF0_REGDATA_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF0_REGDATA_SHIFT) & \
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(TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT)))
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#define TX39_SIBSF0_REGDATA_CLR(cr) \
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((cr) &= ~(TX39_SIBSF0_REGDATA_MASK << TX39_SIBSF0_REGDATA_SHIFT))
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/*
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* SIB Subframe 1 Control Register
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*/
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#define TX39_SIBSF1CTRL_MUTE 0x04000000
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#define TX39_SIBSF1CTRL_MUXL 0x02000000
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#define TX39_SIBSF1CTRL_MUXR 0x01000000
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#define TX39_SIBSF1CTRL_ADCGAINL_SHIFT 20
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#define TX39_SIBSF1CTRL_ADCGAINL_MASK 0xf
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#define TX39_SIBSF1CTRL_ADCGAINL_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINL_SHIFT) & \
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(TX39_SIBSF1CTRL_ADCGAINL_MASK << TX39_SIBSF1CTRL_ADCGAINL_SHIFT)))
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#define TX39_SIBSF1CTRL_ADCGAINR_SHIFT 16
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#define TX39_SIBSF1CTRL_ADCGAINR_MASK 0xf
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#define TX39_SIBSF1CTRL_ADCGAINR_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF1CTRL_ADCGAINR_SHIFT) & \
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(TX39_SIBSF1CTRL_ADCGAINR_MASK << TX39_SIBSF1CTRL_ADCGAINR_SHIFT)))
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#define TX39_SIBSF1CTRL_DACATTNL_SHIFT 8
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#define TX39_SIBSF1CTRL_DACATTNL_MASK 0xf
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#define TX39_SIBSF1CTRL_DACATTNL_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNL_SHIFT) & \
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(TX39_SIBSF1CTRL_DACATTNL_MASK << TX39_SIBSF1CTRL_DACATTNL_SHIFT)))
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#define TX39_SIBSF1CTRL_DACATTNR_SHIFT 4
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#define TX39_SIBSF1CTRL_DACATTNR_MASK 0xf
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#define TX39_SIBSF1CTRL_DACATTNR_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF1CTRL_DACATTNR_SHIFT) & \
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(TX39_SIBSF1CTRL_DACATTNR_MASK << TX39_SIBSF1CTRL_DACATTNR_SHIFT)))
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#define TX39_SIBSF1CTRL_DIGITALOUT_SHIFT 0
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#define TX39_SIBSF1CTRL_DIGITALOUT_MASK 0xf
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#define TX39_SIBSF1CTRL_DIGITALOUT_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT) & \
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(TX39_SIBSF1CTRL_DIGITALOUT_MASK << TX39_SIBSF1CTRL_DIGITALOUT_SHIFT)))
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/*
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* SIB Subframe 1 Status Register
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*/
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#define TX39_SIBSF1STAT_ADCVALID 0x04000000
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#define TX39_SIBSF1STAT_ADCCLIPL 0x02000000
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#define TX39_SIBSF1STAT_ADCCLIPR 0x01000000
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#define TX39_SIBSF1STAT_ERROR_SHIFT 20
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#define TX39_SIBSF1STAT_ERROR_MASK 0xf
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#define TX39_SIBSF1STAT_ERROR_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF1STAT_ERROR_SHIFT) & \
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(TX39_SIBSF1STAT_ERROR_MASK << TX39_SIBSF1STAT_ERROR_SHIFT)))
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#define TX39_SIBSF1STAT_REVISION_SHIFT 16
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#define TX39_SIBSF1STAT_REVISION_MASK 0xf
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#define TX39_SIBSF1STAT_REVISION_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF1STAT_REVISION_SHIFT) & \
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(TX39_SIBSF1STAT_REVISION_MASK << TX39_SIBSF1STAT_REVISION_SHIFT)))
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#define TX39_SIBSF1STAT_DIGITALIN_SHIFT 0
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#define TX39_SIBSF1STAT_DIGITALIN_MASK 0xf
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#define TX39_SIBSF1STAT_DIGITALIN_SET(cr, val) \
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((cr) | (((val) << TX39_SIBSF1STAT_DIGITALIN_SHIFT) & \
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(TX39_SIBSF1STAT_DIGITALIN_MASK << TX39_SIBSF1STAT_DIGITALIN_SHIFT)))
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/*
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* SIB DMA Control Register
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*/
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#define TX39_SIBDMACTRL_SNDBUFF1TIME 0x80000000
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#define TX39_SIBDMACTRL_SNDDMALOOP 0x40000000
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#define TX39_SIBDMACTRL_SNDDMAPTR_SHIFT 18
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#define TX39_SIBDMACTRL_SNDDMAPTR_MASK 0xfff
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#define TX39_SIBDMACTRL_SNDDMAPTR(cr) \
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(((cr) >> TX39_SIBDMACTRL_SNDDMAPTR_SHIFT) & \
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TX39_SIBDMACTRL_SNDDMAPTR_MASK)
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#define TX39_SIBDMACTRL_ENDMARXSND 0x00020000
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#define TX39_SIBDMACTRL_ENDMATXSND 0x00010000
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#define TX39_SIBDMACTRL_TELBUFF1TIME 0x00008000
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#define TX39_SIBDMACTRL_TELDMALOOP 0x00004000
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#define TX39_SIBDMACTRL_TELDMAPTR_SHIFT 2
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#define TX39_SIBDMACTRL_TELDMAPTR_MASK 0xfff
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#define TX39_SIBDMACTRL_TELDMAPTR(cr) \
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(((cr) >> TX39_SIBDMACTRL_TELDMAPTR_SHIFT) & \
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TX39_SIBDMACTRL_TELDMAPTR_MASK)
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#define TX39_SIBDMACTRL_ENDMARXTEL 0x00000002
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#define TX39_SIBDMACTRL_ENDMATXTEL 0x00000001
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