374 lines
11 KiB
C
374 lines
11 KiB
C
/* $NetBSD: if_stereg.h,v 1.4 2007/12/25 18:33:40 perry Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_IF_STEREG_H_
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#define _DEV_PCI_IF_STEREG_H_
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/*
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* Register description for the Sundance Tech. ST-201 10/100
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* Ethernet controller.
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*/
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/*
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* ST-201 buffer fragment descriptor.
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*/
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struct ste_frag {
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uint32_t frag_addr; /* buffer address */
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uint32_t frag_len; /* buffer length */
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} __packed;
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#define FRAG_LEN 0x00001fff /* length mask */
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#define FRAG_LAST (1U << 31) /* last frag in list */
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/*
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* ST-201 Transmit Frame Descriptor. Note the number of fragments
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* here is arbitrary, but we can't exceed 512 bytes of TFD.
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*/
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#define STE_NTXFRAGS 16
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struct ste_tfd {
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uint32_t tfd_next; /* next TFD in list */
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uint32_t tfd_control; /* control bits */
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/* the buffer fragments */
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struct ste_frag tfd_frags[STE_NTXFRAGS];
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} __packed;
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#define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */
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#define TFD_WordAlign_word 2 /* align to word in TxFIFO */
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#define TFD_WordAlign_disable 1 /* disable alignment */
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#define TFD_FrameId(x) ((x) << 2)
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#define TFD_FrameId_MAX 0xff
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#define TFD_FcsAppendDisable (1U << 13)
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#define TFD_TxIndicate (1U << 15)
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#define TFD_TxDMAComplete (1U << 16)
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#define TFD_TxDMAIndicate (1U << 31)
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/*
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* ST-201 Receive Frame Descriptor. Note the number of fragments
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* here is arbitrary (we only use one), but we can't exceed 512
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* bytes of RFD.
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*/
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struct ste_rfd {
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uint32_t rfd_next; /* next RFD in list */
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uint32_t rfd_status; /* status bits */
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struct ste_frag rfd_frag; /* the buffer */
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} __packed;
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#define RFD_RxDMAFrameLen(x) ((x) & FRAG_LEN)
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#define RFD_RxFrameError (1U << 14)
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#define RFD_RxDMAComplete (1U << 15)
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#define RFD_RxFIFOOverrun (1U << 16)
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#define RFD_RxRuntFrame (1U << 17)
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#define RFD_RxAlignmentError (1U << 18)
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#define RFD_RxFCSError (1U << 19)
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#define RFD_RxOversizedFrame (1U << 20)
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#define RFD_DribbleBits (1U << 23)
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#define RFD_RxDMAOverflow (1U << 24)
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#define RFD_ImpliedBufferEnable (1U << 28)
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/*
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* PCI configuration registers used by the ST-201.
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*/
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#define STE_PCI_IOBA (PCI_MAPREG_START + 0x00)
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#define STE_PCI_MMBA (PCI_MAPREG_START + 0x04)
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/*
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* EEPROM offsets.
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*/
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#define STE_EEPROM_ConfigParam 0x00
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#define STE_EEPROM_AsicCtrl 0x02
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#define STE_EEPROM_SubSystemVendorId 0x04
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#define STE_EEPROM_SubSystemId 0x06
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#define STE_EEPROM_StationAddress0 0x10
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#define STE_EEPROM_StationAddress1 0x12
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#define STE_EEPROM_StationAddress2 0x14
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/*
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* The ST-201 register space.
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*/
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#define STE_DMACtrl 0x00 /* 32-bit */
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#define DC_RxDMAHalted (1U << 0)
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#define DC_TxDMACmplReq (1U << 1)
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#define DC_TxDMAHalted (1U << 2)
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#define DC_RxDMAComplete (1U << 3)
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#define DC_TxDMAComplete (1U << 4)
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#define DC_RxDMAHalt (1U << 8)
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#define DC_RxDMAResume (1U << 9)
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#define DC_TxDMAHalt (1U << 10)
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#define DC_TxDMAResume (1U << 11)
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#define DC_TxDMAInProg (1U << 14)
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#define DC_DMAHaltBusy (1U << 15)
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#define DC_RxEarlyEnable (1U << 17)
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#define DC_CountdownSpeed (1U << 18)
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#define DC_CountdownMode (1U << 19)
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#define DC_MWIDisable (1U << 20)
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#define DC_RxDMAOverrunFrame (1U << 22)
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#define DC_CountdownIntEnable (1U << 23)
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#define DC_TargetAbort (1U << 30)
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#define DC_MasterAbort (1U << 31)
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#define STE_TxDMAListPtr 0x04 /* 32-bit */
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#define STE_TxDMABurstThresh 0x08 /* 8-bit */
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#define STE_TxDMAUrgentThresh 0x09 /* 8-bit */
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#define STE_TxDMAPollPeriod 0x0a /* 8-bit */
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#define STE_RxDMAStatus 0x0c /* 32-bit */
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#define RDS_RxDMAFrameLen(x) ((x) & 0x1fff)
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#define RDS_RxFrameError (1U << 14)
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#define RDS_RxDMAComplete (1U << 15)
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#define RDS_RxFIFOOverrun (1U << 16)
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#define RDS_RxRuntFrame (1U << 17)
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#define RDS_RxAlignmentError (1U << 18)
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#define RDS_RxFCSError (1U << 19)
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#define RDS_RxOversizedFrame (1U << 20)
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#define RDS_DribbleBits (1U << 23)
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#define RDS_RxDMAOverflow (1U << 24)
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#define STE_RxDMAListPtr 0x10 /* 32-bit */
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#define STE_RxDMABurstThresh 0x14 /* 8-bit */
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#define STE_RxDMAUrgentThresh 0x15 /* 8-bit */
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#define STE_RxDMAPollPeriod 0x16 /* 8-bit */
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#define STE_DebugCtrl 0x1a /* 16-bit */
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#define DC_GPIO0Ctrl (1U << 0) /* 1 = input */
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#define DC_GPIO1Ctrl (1U << 1) /* 1 = input */
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#define DC_GPIO0 (1U << 2)
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#define DC_GPIO1 (1U << 3)
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#define STE_AsicCtrl 0x30 /* 32-bit */
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#define AC_ExpRomSize (1U << 1) /* 0 = 32K, 1 = 64K */
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#define AC_TxLargeEnable (1U << 2) /* > 2K */
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#define AC_RxLargeEnable (1U << 3) /* > 2K */
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#define AC_ExpRomDisable (1U << 4)
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#define AC_PhySpeed10 (1U << 5)
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#define AC_PhySpeed100 (1U << 6)
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#define AC_PhyMedia(x) (((x) >> 7) & 0x7)
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#define AC_PhyMedia_10T 1
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#define AC_PhyMedia_100T 2
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#define AC_PhyMedia_10_100T 3
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#define AC_PhyMedia_10F 5
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#define AC_PhyMedia_100F 6
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#define AC_PhyMedia_10_100F 7
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#define AC_ForcedConfig(x) (((x) >> 8) & 0x7)
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#define AC_D3ResetDisable (1U << 11)
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#define AC_SpeedupMode (1U << 13)
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#define AC_LEDMode (1U << 14)
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#define AC_RstOutPolarity (1U << 15)
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#define AC_GlobalReset (1U << 16)
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#define AC_RxReset (1U << 17)
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#define AC_TxReset (1U << 18)
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#define AC_DMA (1U << 19)
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#define AC_FIFO (1U << 20)
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#define AC_Network (1U << 21)
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#define AC_Host (1U << 22)
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#define AC_AutoInit (1U << 23)
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#define AC_RstOut (1U << 24)
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#define AC_InterruptRequest (1U << 25)
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#define AC_ResetBusy (1U << 26)
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#define STE_EepromData 0x34 /* 16-bit */
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#define STE_EepromCtrl 0x36 /* 16-bit */
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#define EC_EepromAddress(x) ((x) & 0xff)
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#define EC_EepromOpcode(x) ((x) << 8)
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#define EC_OP_WE 0
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#define EC_OP_W 1
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#define EC_OP_R 2
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#define EC_OP_E 3
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#define EC_EepromBusy (1U << 15)
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#define STE_FIFOCtrl 0x3a /* 16-bit */
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#define FC_RAMTestMode (1U << 0)
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#define FC_RxOverrunFrame (1U << 9)
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#define FC_RxFIFOFull (1U << 11)
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#define FC_Transmitting (1U << 14)
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#define FC_Receiving (1U << 15)
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#define STE_TxStartThresh 0x3c /* 16-bit */
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#define STE_RxEarlyThresh 0x3e /* 16-bit */
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#define STE_ExpRomAddr 0x40 /* 32-bit */
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#define STE_ExpRomData 0x44 /* 8-bit */
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#define STE_WakeEvent 0x45 /* 8-bit */
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#define WE_WakePktEnable (1U << 0)
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#define WE_MagicPktEnable (1U << 1)
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#define WE_LinkEventEnable (1U << 2)
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#define WE_WakePolarity (1U << 3)
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#define WE_WakePktEvent (1U << 4)
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#define WE_MagicPktEvent (1U << 5)
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#define WE_LinkEvent (1U << 6)
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#define WE_WakeOnLanEnable (1U << 7)
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#define STE_TxStatus 0x46 /* 8-bit */
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#define TS_TxReleaseError (1U << 1)
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#define TS_TxStatusOverflow (1U << 2)
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#define TS_MaxCollisions (1U << 3)
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#define TS_TxUnderrun (1U << 4)
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#define TS_TxIndicateReqd (1U << 6)
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#define TS_TxComplete (1U << 7)
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#define STE_TxFrameId 0x47 /* 8-bit */
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#define STE_Countdown 0x48 /* 16-bit */
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#define STE_IntStatusAck 0x4a /* 16-bit */
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#define STE_IntEnable 0x4c /* 16-bit */
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#define IE_HostError (1U << 1)
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#define IE_TxComplete (1U << 2)
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#define IE_MACControlFrame (1U << 3)
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#define IE_RxComplete (1U << 4)
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#define IE_RxEarly (1U << 5)
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#define IE_IntRequested (1U << 6)
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#define IE_UpdateStats (1U << 7)
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#define IE_LinkEvent (1U << 8)
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#define IE_TxDMAComplete (1U << 9)
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#define IE_RxDMAComplete (1U << 10)
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#define STE_IntStatus 0x4e /* 16-bit */
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#define IS_InterruptStatus (1U << 0)
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#define STE_MacCtrl0 0x50 /* 16-bit */
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#define MC0_IFSSelect(x) ((x) << 0)
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#define MC0_FullDuplexEnable (1U << 5)
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#define MC0_RcvLargeFrames (1U << 6)
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#define MC0_FlowControlEnable (1U << 8)
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#define MC0_RcvFCS (1U << 9)
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#define MC0_FIFOLoopback (1U << 10)
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#define MC0_MACLoopback (1U << 11)
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#define STE_MacCtrl1 0x52 /* 16-bit */
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#define MC1_CollsionDetect (1U << 0)
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#define MC1_CarrierSense (1U << 1)
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#define MC1_TxInProg (1U << 2)
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#define MC1_TxError (1U << 3)
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#define MC1_StatisticsEnable (1U << 5)
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#define MC1_StatisticsDisable (1U << 6)
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#define MC1_StatisticsEnabled (1U << 7)
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#define MC1_TxEnable (1U << 8)
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#define MC1_TxDisable (1U << 9)
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#define MC1_TxEnabled (1U << 10)
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#define MC1_RxEnable (1U << 11)
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#define MC1_RxDisable (1U << 12)
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#define MC1_RxEnabled (1U << 13)
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#define MC1_Paused (1U << 14)
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#define STE_StationAddress0 0x54 /* 16-bit */
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#define STE_StationAddress1 0x56 /* 16-bit */
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#define STE_StationAddress2 0x58 /* 16-bit */
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#define STE_MaxFrameSize 0x5a /* 16-bit */
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#define STE_ReceiveMode 0x5c /* 8-bit */
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#define RM_ReceiveUnicast (1U << 0)
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#define RM_ReceiveMulticast (1U << 1)
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#define RM_ReceiveBroadcast (1U << 2)
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#define RM_ReceiveAllFrames (1U << 3)
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#define RM_ReceiveMulticastHash (1U << 4)
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#define RM_ReceiveIPMulticast (1U << 5)
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#define STE_TxReleaseThresh 0x5d /* 8-bit */
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#define STE_PhyCtrl 0x5e /* 8-bit */
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#define PC_MgmtClk (1U << 0)
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#define PC_MgmtData (1U << 1)
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#define PC_MgmtDir (1U << 2) /* 1 = MAC->Phy */
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#define PC_DisableClk25 (1U << 3)
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#define PC_PhyDuplexPolarity (1U << 4)
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#define PC_PhyDuplexStatus (1U << 5)
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#define PC_PhySpeedStatus (1U << 6)
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#define PC_PhyLinkStatus (1U << 7)
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#define STE_HashTable0 0x60 /* 16-bit */
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#define STE_HashTable1 0x62 /* 16-bit */
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#define STE_HashTable2 0x64 /* 16-bit */
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#define STE_HashTable3 0x66 /* 16-bit */
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#define STE_OctetsReceivedOk0 0x68 /* 16-bit */
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#define STE_OctetsReceivedOk1 0x6a /* 16-bit */
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#define STE_OctetsTransmittedOk0 0x6c /* 16-bit */
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#define STE_OctetsTransmittedOk1 0x6e /* 16-bit */
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#define STE_FramesTransmittedOK 0x70 /* 16-bit */
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#define STE_FramesReceivedOK 0x72 /* 16-bit */
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#define STE_CarrierSenseErrors 0x74 /* 8-bit */
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#define STE_LateCollisions 0x75 /* 8-bit */
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#define STE_MultipleColFrames 0x76 /* 8-bit */
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#define STE_SingleColFrames 0x77 /* 8-bit */
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#define STE_FramesWDeferredXmt 0x78 /* 8-bit */
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#define STE_FramesLostRxErrors 0x79 /* 8-bit */
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#define STE_FramesWExDeferral 0x7a /* 8-bit */
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#define STE_FramesXbortXSColls 0x7b /* 8-bit */
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#define STE_BcstFramesXmtdOk 0x7c /* 8-bit */
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#define STE_BcstFramesRcvdOk 0x7d /* 8-bit */
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#define STE_McstFramesXmtdOk 0x7e /* 8-bit */
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#define STE_McstFramesRcvdOk 0x7f /* 8-bit */
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#endif /* _DEV_PCI_IF_STEREG_H_ */
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