374 lines
11 KiB
ArmAsm
374 lines
11 KiB
ArmAsm
/* vector.s */
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#include "i386/isa/icu.h"
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#include "i386/isa/isa.h"
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#include "vector.h"
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#define ICU_EOI 0x20 /* XXX - define elsewhere */
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) / 8)
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#ifndef AUTO_EOI_1
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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FASTER_NOP ; /* ... ASAP ... */ \
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outb %al,$IO_ICU1 /* ... to clear in service bit */
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#else /* AUTO_EOI_1 */
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#define ENABLE_ICU1 /* we now use auto-EOI to reduce i/o */
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#endif
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#ifndef AUTO_EOI_2
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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FASTER_NOP ; \
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outb %al,$IO_ICU2 ; /* but do second icu first */ \
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FASTER_NOP ; \
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outb %al,$IO_ICU1 /* then first icu */
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#else /* AUTO_EOI_2 */
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#define ENABLE_ICU1_AND_2 /* data sheet says no auto-EOI on slave ... */
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/* ... but it sometimes works */
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#endif
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/*
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* Macros for interrupt interrupt entry, call to handler, and exit.
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*
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* XXX - the interrupt frame is set up to look like a trap frame. This is
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* usually a waste of time. The only interrupt handlers that want a frame
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* are the clock handler (it wants a clock frame), the npx handler (it's
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* easier to do right all in assembler). The interrupt return routine
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* needs a trap frame for rare AST's (it could easily convert the frame).
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* The direct costs of setting up a trap frame are two pushl's (error
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* code and trap number), an addl to get rid of these, and pushing and
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* popping the call-saved regs %esi, %edi and %ebp twice, The indirect
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* costs are making the driver interface nonuniform so unpending of
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* interrupts is more complicated and slower (call_driver(unit) would
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* be easier than ensuring an interrupt frame for all handlers. Finally,
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* there are some struct copies in the npx handler and maybe in the clock
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* handler that could be avoided by working more with pointers to frames
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* instead of frames.
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*
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* XXX - should we do a cld on every system entry to avoid the requirement
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* for scattered cld's?
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*
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* Coding notes for *.s:
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*
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* If possible, avoid operations that involve an operand size override.
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* Word-sized operations might be smaller, but the operand size override
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* makes them slower on on 486's and no faster on 386's unless perhaps
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* the instruction pipeline is depleted. E.g.,
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*
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* Use movl to seg regs instead of the equivalent but more descriptive
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* movw - gas generates an irelevant (slower) operand size override.
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*
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* Use movl to ordinary regs in preference to movw and especially
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* in preference to movz[bw]l. Use unsigned (long) variables with the
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* top bits clear instead of unsigned short variables to provide more
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* opportunities for movl.
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*
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* If possible, use byte-sized operations. They are smaller and no slower.
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*
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* Use (%reg) instead of 0(%reg) - gas generates larger code for the latter.
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*
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* If the interrupt frame is made more flexible, INTR can push %eax first
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* and decide the ipending case with less overhead, e.g., by avoiding
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* loading segregs.
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*/
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#define FAST_INTR(unit, irq_num, id_num, handler, enable_icus) \
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pushl %eax ; /* save only call-used registers */ \
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pushl %ecx ; \
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pushl %edx ; \
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pushl %ds ; \
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pushl %es ; \
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movl $KDSEL,%eax ; \
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movl %ax,%ds ; \
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movl %ax,%es ; \
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SHOW_CLI ; /* although it interferes with "ASAP" */ \
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pushl $unit ; \
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call handler ; /* do the work ASAP */ \
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enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
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addl $4,%esp ; \
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incl _cnt+V_INTR ; /* book-keeping can wait */ \
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COUNT_INTR(_intrcnt_actv, id_num) ; \
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SHOW_STI ; \
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popl %es ; \
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popl %ds ; \
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popl %edx; \
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popl %ecx; \
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popl %eax; \
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iret
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#define INTR(unit, irq_num, id_num, mask, handler, icu, enable_icus, reg, stray) \
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pushl $0 ; /* dummy error code */ \
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pushl $T_ASTFLT ; \
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pushal ; \
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pushl %ds ; /* save our data and extra segments ... */ \
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pushl %es ; \
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movl $KDSEL,%eax ; /* ... and reload with kernel's own ... */ \
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movl %ax,%ds ; /* ... early in case SHOW_A_LOT is on */ \
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movl %ax,%es ; \
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SHOW_CLI ; /* interrupt did an implicit cli */ \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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SHOW_IMEN ; \
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FASTER_NOP ; \
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outb %al,$icu+1 ; \
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enable_icus ; \
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incl _cnt+V_INTR ; /* tally interrupts */ \
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movl _cpl,%eax ; \
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testb $IRQ_BIT(irq_num),%reg ; \
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jne 2f ; \
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1: ; \
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COUNT_INTR(_intrcnt_actv, id_num) ; \
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movl _cpl,%eax ; \
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pushl %eax ; \
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pushl $unit ; \
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orl mask,%eax ; \
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movl %eax,_cpl ; \
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SHOW_CPL ; \
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SHOW_STI ; \
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sti ; \
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call handler ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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andb $~IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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SHOW_IMEN ; \
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FASTER_NOP ; \
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outb %al,$icu+1 ; \
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jmp doreti ; \
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; \
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ALIGN_TEXT ; \
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2: ; \
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COUNT_EVENT(_intrcnt_pend, id_num) ; \
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movl $1b,%eax ; /* register resume address */ \
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/* XXX - someday do it at attach time */ \
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movl %eax,Vresume + (irq_num) * 4 ; \
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orb $IRQ_BIT(irq_num),_ipending + IRQ_BYTE(irq_num) ; \
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SHOW_IPENDING ; \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp ; \
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iret
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/*
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* vector.h has defined a macro 'BUILD_VECTORS' containing a big list of info
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* about vectors, including a submacro 'BUILD_VECTOR' that operates on the
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* info about each vector. We redefine 'BUILD_VECTOR' to expand the info
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* in different ways. Here we expand it to a list of interrupt handlers.
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* This order is of course unimportant. Elsewhere we expand it to inline
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* linear search code for which the order is a little more important and
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* concatenating the code with no holes is very important.
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*
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* XXX - now there is BUILD_FAST_VECTOR as well as BUILD_VECTOR.
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*
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* The info consists of the following items for each vector:
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*
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* name (identifier): name of the vector; used to build labels
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* unit (expression): unit number to call the device driver with
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* irq_num (number): number of the IRQ to handled (0-15)
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* id_num (number): uniq numeric id for handler (assigned by config)
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* mask (blank-ident): priority mask used
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* handler (blank-ident): interrupt handler to call
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* icu_num (number): (1 + irq_num / 8) converted for label building
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* icu_enables (number): 1 for icu_num == 1, 1_AND_2 for icu_num == 2
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* reg (blank-ident): al for icu_num == 1, ah for icu_num == 2
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*
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* 'irq_num' is converted in several ways at config time to get around
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* limitations in cpp. The macros have blanks after commas iff they would
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* not mess up identifiers and numbers.
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*/
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#undef BUILD_FAST_VECTOR
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#define BUILD_FAST_VECTOR(name, unit, irq_num, id_num, mask, handler, \
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icu_num, icu_enables, reg) \
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.globl handler ; \
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.text ; \
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.globl _X/**/name ; \
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SUPERALIGN_TEXT ; \
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_X/**/name: ; \
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FAST_INTR(unit, irq_num, id_num, handler, ENABLE_ICU/**/icu_enables)
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#undef BUILD_VECTOR
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#define BUILD_VECTOR(name, unit, irq_num, id_num, mask, handler, \
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icu_num, icu_enables, reg) \
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.globl handler ; \
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.text ; \
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.globl _X/**/name ; \
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SUPERALIGN_TEXT ; \
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_X/**/name: ; \
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INTR(unit,irq_num,id_num, mask, handler, IO_ICU/**/icu_num, \
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ENABLE_ICU/**/icu_enables, reg,)
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BUILD_VECTORS
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/* hardware interrupt catcher (IDT 32 - 47) */
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.globl _isa_strayintr
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#define STRAYINTR(irq_num, icu_num, icu_enables, reg) \
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IDTVEC(intr/**/irq_num) ; \
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INTR(irq_num,irq_num,irq_num, _highmask, _isa_strayintr, \
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IO_ICU/**/icu_num, ENABLE_ICU/**/icu_enables, reg,stray)
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/*
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* XXX - the mask (1 << 2) == IRQ_SLAVE will be generated for IRQ 2, instead
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* of the mask IRQ2 (defined as IRQ9 == (1 << 9)). But IRQ 2 "can't happen".
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* In fact, all stray interrupts "can't happen" except for bugs. The
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* "stray" IRQ 7 is documented behaviour of the 8259. It happens when there
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* is a glitch on any of its interrupt inputs. Does it really interrupt when
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* IRQ 7 is masked?
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*
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* XXX - unpend doesn't work for these, it sends them to the real handler.
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*
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* XXX - the race bug during initialization may be because I changed the
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* order of switching from the stray to the real interrupt handler to before
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* enabling interrupts. The old order looked unsafe but maybe it is OK with
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* the stray interrupt handler installed. But these handlers only reduce
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* the window of vulnerability - it is still open at the end of
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* isa_configure().
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*
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* XXX - many comments are stale.
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*/
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STRAYINTR(0,1,1, al)
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STRAYINTR(1,1,1, al)
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STRAYINTR(2,1,1, al)
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STRAYINTR(3,1,1, al)
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STRAYINTR(4,1,1, al)
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STRAYINTR(5,1,1, al)
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STRAYINTR(6,1,1, al)
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STRAYINTR(8,2,1_AND_2, ah)
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STRAYINTR(9,2,1_AND_2, ah)
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STRAYINTR(10,2,1_AND_2, ah)
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STRAYINTR(11,2,1_AND_2, ah)
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STRAYINTR(12,2,1_AND_2, ah)
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STRAYINTR(13,2,1_AND_2, ah)
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STRAYINTR(14,2,1_AND_2, ah)
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STRAYINTR(15,2,1_AND_2, ah)
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IDTVEC(intrdefault)
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STRAYINTR(7,1,1, al) /* XXX */
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#if 0
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INTRSTRAY(255, _highmask, 255) ; call _isa_strayintr ; INTREXIT2
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#endif
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/*
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* These are the interrupt counters, I moved them here from icu.s so that
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* they are with the name table. rgrimes
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*
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* There are now lots of counters, this has been redone to work with
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* Bruce Evans intr-0.1 code, which I modified some more to make it all
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* work with vmstat.
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*/
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.data
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Vresume: .space 16 * 4 /* where to resume intr handler after unpend */
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.globl _intrcnt
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_intrcnt: /* used by vmstat to calc size of table */
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.globl _intrcnt_bad7
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_intrcnt_bad7: .space 4 /* glitches on irq 7 */
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.globl _intrcnt_bad15
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_intrcnt_bad15: .space 4 /* glitches on irq 15 */
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.globl _intrcnt_stray
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_intrcnt_stray: .space 4 /* total count of stray interrupts */
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.globl _intrcnt_actv
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_intrcnt_actv: .space NR_REAL_INT_HANDLERS * 4 /* active interrupts */
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#ifdef INTR_DEBUG
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.globl _intrcnt_pend
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_intrcnt_pend: .space NR_REAL_INT_HANDLERS * 4 /* pending interrupts */
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.globl _intrcnt_spl
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_intrcnt_spl: .space 32 * 4 /* XXX 32 should not be hard coded ? */
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.globl _intrcnt_show
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_intrcnt_show: .space 8 * 4 /* XXX 16 should not be hard coded ? */
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#endif /* INTR_DEBUG */
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.globl _eintrcnt
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_eintrcnt: /* used by vmstat to calc size of table */
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/*
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* Build the interrupt name table for vmstat
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*/
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#undef BUILD_FAST_VECTOR
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#define BUILD_FAST_VECTOR BUILD_VECTOR
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#undef BUILD_VECTOR
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#define BUILD_VECTOR(name, unit, irq_num, id_num, mask, handler, \
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icu_num, icu_enables, reg) \
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.ascii "name irq" ; \
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.asciz "irq_num"
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/*
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* XXX - use the STRING and CONCAT macros from <sys/cdefs.h> to stringize
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* and concatenate names above and elsewhere.
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*/
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.text
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.globl _intrnames, _eintrnames
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_intrnames:
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BUILD_VECTOR(bad,,7,,,,,,)
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BUILD_VECTOR(bad,,15,,,,,,)
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BUILD_VECTOR(stray,,,,,,,,)
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BUILD_VECTORS
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#ifdef INTR_DEBUG
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#undef BUILD_FAST_VECTOR
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#define BUILD_FAST_VECTOR BUILD_VECTOR
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#undef BUILD_VECTOR
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#define BUILD_VECTOR(name, unit, irq_num, id_num, mask, handler, \
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icu_num, icu_enables, reg) \
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.asciz "name pend"
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BUILD_VECTORS
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/*
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* now the spl names
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*/
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.asciz "unpend_v"
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.asciz "doreti"
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.asciz "p0!ni"
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.asciz "!p0!ni"
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.asciz "p0ni"
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.asciz "netisr_raw"
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.asciz "netisr_ip"
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.asciz "netisr_imp"
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.asciz "netisr_ns"
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.asciz "softclock"
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.asciz "trap"
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.asciz "doreti_exit2"
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.asciz "splbio"
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.asciz "splclock"
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.asciz "splhigh"
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.asciz "splimp"
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.asciz "splnet"
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.asciz "splsoftclock"
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.asciz "spltty"
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.asciz "spl0"
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.asciz "netisr_raw2"
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.asciz "netisr_ip2"
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.asciz "splx"
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.asciz "splx!0"
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.asciz "unpend_V"
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.asciz "netisr_iso"
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.asciz "netisr_imp2"
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.asciz "netisr_ns2"
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.asciz "netisr_iso2"
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.asciz "spl29" /* spl29-spl31 are spares */
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.asciz "spl30"
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.asciz "spl31"
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/*
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* now the mask names
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*/
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.asciz "cli"
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.asciz "cpl"
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.asciz "imen"
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.asciz "ipending"
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.asciz "sti"
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.asciz "mask5" /* mask5-mask7 are spares */
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.asciz "mask6"
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.asciz "mask7"
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#endif /* INTR_DEBUG */
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_eintrnames:
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