367 lines
9.2 KiB
C
367 lines
9.2 KiB
C
/* $NetBSD: ralink_intr.c,v 1.5 2016/10/05 15:54:58 ryo Exp $ */
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/*-
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* Copyright (c) 2011 CradlePoint Technology, Inc.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY CRADLEPOINT TECHNOLOGY, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define __INTR_PRIVATE
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ralink_intr.c,v 1.5 2016/10/05 15:54:58 ryo Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <mips/locore.h>
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#include <mips/ralink/ralink_reg.h>
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#include <mips/ralink/ralink_var.h>
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static int ra_pic_intr(void *arg);
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/*
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* evbmips spl integration:
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* this is a mask of bits to clear in the SR when we go to a
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* given hardware interrupt priority level.
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*/
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static const struct ipl_sr_map ralink_ipl_sr_map = {
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.sr_bits = {
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[IPL_NONE] = 0,
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[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
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[IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
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[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
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[IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
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[IPL_VM] = MIPS_INT_MASK ^ MIPS_INT_MASK_5,
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[IPL_SCHED] = MIPS_INT_MASK,
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[IPL_DDB] = MIPS_INT_MASK,
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[IPL_HIGH] = MIPS_INT_MASK,
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},
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};
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/*
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* RT3052 Interrupt Block Definitions
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*
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* HW_INT0 - Low Priority Chip Interrupts (Lowest Priority)
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* HW_INT1 - High Priority Chip Interrupts
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* HW_INT2 - PCIe/PCI (3883 only)
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* HW_INT3 - Frame Engine
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* HW_INT4 - 802.11n NIC
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* HW_INT5 - Timer Interrupt (Highest Priority)
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*
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* HW_INT0 and HW_INT1 can be configured to fire with any of the other
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* interrupts on chip. They can be masked for either INT0 or INT1
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* but not both.
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*
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* SYSCTL
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* TIMER0
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* WDTIMER
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* ILLACC
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* PCM
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* UARTF
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* PIO
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* DMA
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* NAND
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* PERF
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* I2S
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* UARTL
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* ETHSW
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* USB
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*/
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struct ra_intr {
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LIST_HEAD(, evbmips_intrhand) intr_list;
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struct evcnt intr_evcnt;
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};
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/*
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* ordering for ra_intrtab[] and ra_intr_names[]
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* corresponds to the RA_IRQ_* definitions
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* which include the CPU intrs and the PIC intrs
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*/
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static struct ra_intr ra_intrtab[RA_IRQ_MAX];
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static const char * const ra_intr_names[RA_IRQ_MAX] = {
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/* CPU interrupts */
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[RA_IRQ_LOW] = "intr 0 (lowpri)",
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[RA_IRQ_HIGH] = "intr 1 (highpri)",
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[RA_IRQ_PCI] = "intr 2 (pci)",
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[RA_IRQ_FENGINE]= "intr 3 (frame)",
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[RA_IRQ_WLAN] = "intr 4 (wlan)",
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[RA_IRQ_TIMER] = "intr 5 (timer)",
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/* Interrupt controller */
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[RA_IRQ_SYSCTL] = "intc sysctl",
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[RA_IRQ_TIMER0] = "intc timer0",
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[RA_IRQ_WDOG] = "intc wdog",
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[RA_IRQ_ILLACC] = "intc illacc",
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[RA_IRQ_PCM] = "intc pcm",
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[RA_IRQ_UARTF] = "intc uartf",
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[RA_IRQ_PIO] = "intc gpio",
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[RA_IRQ_DMA] = "intc dma",
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[RA_IRQ_NAND] = "intc nand",
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[RA_IRQ_PERF] = "intc pef",
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[RA_IRQ_I2S] = "intc i2s",
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[RA_IRQ_SPI] = "intc spi",
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[RA_IRQ_UARTL] = "intc uartl",
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[RA_IRQ_CRYPTO] = "intc crypto",
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[RA_IRQ_SDHC] = "intc sdhc",
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[RA_IRQ_R2P] = "intc r2p",
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[RA_IRQ_ETHSW] = "intc ethsw",
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[RA_IRQ_USB] = "intc usb",
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[RA_IRQ_UDEV] = "intc udev",
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[RA_IRQ_UART1] = "intc uart1",
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[RA_IRQ_UART2] = "intc uart2",
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};
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/* determine if irq belongs to the PIC */
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#define PIC_IRQ_P(irq) ((irq) > RA_IRQ_TIMER)
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/* map the IRQ num to PIC reg bits */
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static const uint8_t irq2bit[RA_IRQ_MAX] = {
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/* CPU interrupts */
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[RA_IRQ_LOW] = -1,
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[RA_IRQ_HIGH] = -1,
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[RA_IRQ_PCI] = -1,
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[RA_IRQ_FENGINE]= -1,
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[RA_IRQ_WLAN] = -1,
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[RA_IRQ_TIMER] = -1,
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/* Interrupt controller */
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[RA_IRQ_SYSCTL] = INT_SYSCTL,
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[RA_IRQ_TIMER0] = INT_TIMER0,
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[RA_IRQ_WDOG] = INT_WDOG,
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[RA_IRQ_ILLACC] = INT_ILLACC,
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[RA_IRQ_PCM] = INT_PCM,
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[RA_IRQ_UARTF] = INT_UARTF,
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[RA_IRQ_PIO] = INT_PIO,
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[RA_IRQ_DMA] = INT_DMA,
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[RA_IRQ_NAND] = INT_NAND,
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[RA_IRQ_PERF] = INT_PERF,
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[RA_IRQ_I2S] = INT_I2S,
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[RA_IRQ_SPI] = INT_SPI,
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[RA_IRQ_UARTL] = INT_UARTL,
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#ifdef INT_UART1
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[RA_IRQ_UART1] = INT_UART1,
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#endif
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#ifdef INT_UART2
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[RA_IRQ_UART2] = INT_UART2,
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#endif
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[RA_IRQ_CRYPTO] = INT_CRYPTO,
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[RA_IRQ_SDHC] = INT_SDHC,
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[RA_IRQ_R2P] = INT_R2P,
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[RA_IRQ_ETHSW] = INT_ETHSW,
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[RA_IRQ_USB] = INT_USB,
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[RA_IRQ_UDEV] = INT_UDEV
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};
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/* map the PIC reg bits to IRQ num */
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static const uint8_t bit2irq[32] = {
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[INT_SYSCTL] = RA_IRQ_SYSCTL,
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[INT_TIMER0] = RA_IRQ_TIMER0,
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[INT_WDOG] = RA_IRQ_WDOG,
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[INT_ILLACC] = RA_IRQ_ILLACC,
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[INT_PCM] = RA_IRQ_PCM,
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[INT_UARTF] = RA_IRQ_UARTF,
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[INT_PIO] = RA_IRQ_PIO,
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[INT_DMA] = RA_IRQ_DMA,
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[INT_NAND] = RA_IRQ_NAND,
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[INT_PERF] = RA_IRQ_PERF,
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[INT_I2S] = RA_IRQ_I2S,
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[INT_SPI] = RA_IRQ_SPI,
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[INT_UARTL] = RA_IRQ_UARTL,
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#ifdef INT_UART1
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[INT_UART1] = RA_IRQ_UART1,
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#endif
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#ifdef INT_UART2
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[INT_UART2] = RA_IRQ_UART2,
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#endif
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[INT_CRYPTO] = RA_IRQ_CRYPTO,
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[INT_SDHC] = RA_IRQ_SDHC,
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[INT_R2P] = RA_IRQ_R2P,
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[INT_ETHSW] = RA_IRQ_ETHSW,
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[INT_USB] = RA_IRQ_USB,
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[INT_UDEV] = RA_IRQ_UDEV
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};
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static inline uint32_t
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intctl_read(u_int offset)
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{
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return *RA_IOREG_VADDR(RA_INTCTL_BASE, offset);
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}
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static inline void
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intctl_write(u_int offset, uint32_t val)
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{
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*RA_IOREG_VADDR(RA_INTCTL_BASE, offset) = val;
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}
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void
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evbmips_intr_init(void)
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{
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ipl_sr_map = ralink_ipl_sr_map;
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for (int irq=0; irq < RA_IRQ_MAX; irq++) {
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LIST_INIT(&ra_intrtab[irq].intr_list);
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if (PIC_IRQ_P(irq)) {
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evcnt_attach_dynamic(&ra_intrtab[irq].intr_evcnt,
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EVCNT_TYPE_INTR, NULL, "pic",
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ra_intr_names[irq]);
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} else {
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evcnt_attach_dynamic(&ra_intrtab[irq].intr_evcnt,
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EVCNT_TYPE_INTR, NULL, "cpu0",
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ra_intr_names[irq]);
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}
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}
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/*
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* make sure we start without any misc interrupts enabled,
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* but the block enabled
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*/
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intctl_write(RA_INTCTL_DISABLE, ~0);
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intctl_write(RA_INTCTL_ENABLE, INT_GLOBAL_EN);
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/*
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* establish the low/high priority cpu interrupts.
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* note here we pass the value of the priority as the argument
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* so it is passed to ra_pic_intr() correctly.
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*/
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ra_intr_establish(RA_IRQ_HIGH, ra_pic_intr,
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(void *)1, 1);
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ra_intr_establish(RA_IRQ_LOW, ra_pic_intr,
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(void *)0, 0);
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}
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void *
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ra_intr_establish(int intr, int (*func)(void *), void *arg, int priority)
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{
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struct evbmips_intrhand *ih;
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if ((ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT)) == NULL) {
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KASSERTMSG(0, "%s: cannot malloc intrhand", __func__);
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return NULL;
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}
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ih->ih_func = func;
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ih->ih_arg = arg;
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ih->ih_irq = intr;
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const int s = splhigh();
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LIST_INSERT_HEAD(&ra_intrtab[intr].intr_list, ih, ih_q);
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if (PIC_IRQ_P(intr)) {
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/* irq belongs to the PIC */
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uint32_t r;
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r = intctl_read(RA_INTCTL_TYPE);
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r |= (priority << irq2bit[intr]);
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intctl_write(RA_INTCTL_TYPE, r);
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r = intctl_read(RA_INTCTL_ENABLE);
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r |= (1 << irq2bit[intr]);
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intctl_write(RA_INTCTL_ENABLE, r);
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}
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splx(s);
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return ih;
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}
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void
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ra_intr_disestablish(void *arg)
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{
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struct evbmips_intrhand * const ih = arg;
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const int s = splhigh();
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LIST_REMOVE(ih, ih_q);
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if (PIC_IRQ_P(ih->ih_irq) &&
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LIST_EMPTY(&ra_intrtab[ih->ih_irq].intr_list)) {
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uint32_t r;
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r = intctl_read(RA_INTCTL_DISABLE);
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r &= ~(1 << irq2bit[ih->ih_irq]);
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intctl_write(RA_INTCTL_DISABLE, r);
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}
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splx(s);
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free(ih, M_DEVBUF);
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}
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/*
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* ra_pic_intr - service PIC interrupts
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*
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* caller handles priority by the calling this function w/ PRI_HIGH first
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*/
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static int
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ra_pic_intr(void *arg)
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{
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const int priority = (intptr_t)arg;
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const u_int off = (priority == 0) ?
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RA_INTCTL_IRQ0STAT : RA_INTCTL_IRQ1STAT;
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uint32_t pending = intctl_read(off);
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while (pending != 0) {
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const u_int bitno = 31 - __builtin_clz(pending);
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pending ^= (1 << bitno);
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const int irq = bit2irq[bitno];
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KASSERT(PIC_IRQ_P(irq));
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ra_intrtab[irq].intr_evcnt.ev_count++;
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struct evbmips_intrhand *ih;
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LIST_FOREACH(ih, &ra_intrtab[irq].intr_list, ih_q)
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(*ih->ih_func)(ih->ih_arg);
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}
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return 1;
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}
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/*
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* evbmips_iointr - process CPU interrupts
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*
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* we only see IRQ 4..0 here as IRQ 5 is handled
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* in the generic MIPS code for the timer
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*/
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void
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evbmips_iointr(int ipl, uint32_t ipending, struct clockframe *cf)
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{
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while (ipending != 0) {
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const u_int bitno = 31 - __builtin_clz(ipending);
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ipending ^= (1 << bitno);
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const int irq = bitno - (31 - __builtin_clz(MIPS_INT_MASK_0));
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KASSERT(!PIC_IRQ_P(irq));
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ra_intrtab[irq].intr_evcnt.ev_count++;
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struct evbmips_intrhand *ih;
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LIST_FOREACH(ih, &ra_intrtab[irq].intr_list, ih_q)
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(*ih->ih_func)(ih->ih_arg);
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}
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}
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