424 lines
11 KiB
C
424 lines
11 KiB
C
/* $NetBSD: obio.c,v 1.11 2012/10/27 17:17:47 chs Exp $ */
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/*
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* Copyright (c) 2002, 2003, 2005 Genetec corp. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec corp.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corp. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/reboot.h>
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#include <machine/cpu.h>
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#include <sys/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <arm/mainbus/mainbus.h>
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#include <arm/xscale/pxa2x0cpu.h>
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#include <arm/xscale/pxa2x0reg.h>
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#include <arm/xscale/pxa2x0var.h>
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#include <arm/xscale/pxa2x0_gpio.h>
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#include <arm/sa11x0/sa11x0_var.h>
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#include <evbarm/g42xxeb/g42xxeb_reg.h>
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#include <evbarm/g42xxeb/g42xxeb_var.h>
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#include "locators.h"
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/* prototypes */
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static int obio_match(device_t, cfdata_t, void *);
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static void obio_attach(device_t, device_t, void *);
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static int obio_search(device_t, cfdata_t, const int *, void *);
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static int obio_print(void *, const char *);
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/* attach structures */
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CFATTACH_DECL_NEW(obio, sizeof(struct obio_softc), obio_match, obio_attach,
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NULL, NULL);
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static int
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obio_spurious(void *arg)
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{
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int irqno = (int)arg;
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printf("Spurious interrupt %d on On-board peripheral", irqno);
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return 1;
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}
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/*
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* interrupt handler for GPIO0 (on-board peripherals)
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*
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* On G4250ebx, 10 interrupts are ORed through on-board logic,
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* and routed to GPIO0 of PXA250 processor.
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*/
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static int
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obio_intr(void *arg)
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{
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int irqno, pending;
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struct obio_softc *sc = (struct obio_softc *)arg;
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int n=0;
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#define get_pending(sc) \
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(bus_space_read_2( sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTSTS1) \
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& ~(sc->sc_intr_pending|sc->sc_intr_mask))
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#ifdef DEBUG
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printf("obio_intr: pend=%x, mask=%x, pend=%x, mask=%x\n",
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bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTSTS1),
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bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTMASK),
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sc->sc_intr_pending,
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sc->sc_intr_mask);
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#endif
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for (pending = get_pending(sc);
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(irqno = find_first_bit(pending)) >= 0;
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pending = get_pending(sc)) {
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/* reset pending bit */
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bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh,
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G42XXEB_INTSTS1, ~(1<<irqno));
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#if 0
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if (sc->sc_handler[irqno].level > saved_spl_level) {
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int spl_save = _splraise(sc->sc_handler[irqno].level);
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(* sc->sc_handler[irqno].func)(
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sc->sc_handler[irqno].arg);
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splx(spl_save);
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}
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else
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#endif
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{
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int psw = disable_interrupts(I32_bit); /* XXX */
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/* mask this interrupt until software
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interrupt is handled. */
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sc->sc_intr_pending |= (1U<<irqno);
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obio_update_intrmask(sc);
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restore_interrupts(psw);
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++n;
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}
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#ifdef DIAGNOSTIC
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if (n > 1000)
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panic("obio_intr: stayed too long");
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#endif
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}
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if (n > 0) {
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/* handle it later */
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softint_schedule(sc->sc_si);
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}
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/* GPIO interrupt is edge triggered. make a pulse
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to let Cotulla notice when other interrupts are
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still pending */
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bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh,
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G42XXEB_INTMASK, 0xffff);
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obio_update_intrmask(sc);
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return 1;
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}
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static void
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obio_softint(void *arg)
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{
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struct obio_softc *sc = (struct obio_softc *)arg;
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int irqno;
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int spl_save = curcpl();
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int psw;
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psw = disable_interrupts(I32_bit);
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while ((irqno = find_first_bit(sc->sc_intr_pending)) >= 0) {
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sc->sc_intr_pending &= ~(1U<<irqno);
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restore_interrupts(psw);
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_splraise(sc->sc_handler[irqno].level);
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(* sc->sc_handler[irqno].func)(
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sc->sc_handler[irqno].arg);
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splx(spl_save);
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psw = disable_interrupts(I32_bit);
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}
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/* assert(sc->sc_intr_pending==0) */
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bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh,
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G42XXEB_INTMASK, 0xffff);
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obio_update_intrmask(sc);
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restore_interrupts(psw);
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}
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/*
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* int obio_print(void *aux, const char *name)
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* print configuration info for children
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*/
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static int
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obio_print(void *aux, const char *name)
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{
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struct obio_attach_args *oba = (struct obio_attach_args*)aux;
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if (oba->oba_addr != OBIOCF_ADDR_DEFAULT)
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aprint_normal(" addr 0x%lx", oba->oba_addr);
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if (oba->oba_intr > 0)
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aprint_normal(" intr %d", oba->oba_intr);
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return (UNCONF);
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}
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int
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obio_match(device_t parent, cfdata_t match, void *aux)
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{
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return 1;
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}
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void
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obio_attach(device_t parent, device_t self, void *aux)
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{
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struct obio_softc *sc = device_private(self);
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struct sa11x0_attach_args *sa = aux;
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bus_space_tag_t iot = sa->sa_iot;
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int i;
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uint16_t reg;
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sc->sc_dev = self;
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/* tweak memory access timing for CS3.
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the value set by redboot is too slow */
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if (bus_space_map(iot, PXA2X0_MEMCTL_BASE, PXA2X0_MEMCTL_SIZE, 0,
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&sc->sc_memctl_ioh))
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goto fail;
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bus_space_write_4(iot, sc->sc_memctl_ioh, MEMCTL_MSC1,
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(0xffff & bus_space_read_4(iot, sc->sc_memctl_ioh, MEMCTL_MSC1))
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| (0x6888 << 16));
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/* Map on-board FPGA registers */
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sc->sc_iot = iot;
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if (bus_space_map(iot, G42XXEB_PLDREG_BASE, G42XXEB_PLDREG_SIZE,
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0, &(sc->sc_obioreg_ioh)))
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goto fail;
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/*
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* Mask all interrupts.
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* They are later unmasked at each device's attach routine.
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*/
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sc->sc_intr_mask = 0xffff;
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bus_space_write_2(iot, sc->sc_obioreg_ioh, G42XXEB_INTMASK,
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sc->sc_intr_mask );
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#if 0
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sc->sc_intr = 8; /* GPIO0 */
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#endif
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sc->sc_intr_pending = 0;
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for (i=0; i < G42XXEB_N_INTS; ++i) {
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sc->sc_handler[i].func = obio_spurious;
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sc->sc_handler[i].arg = (void *)i;
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}
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obio_peripheral_reset(sc, 1, 0);
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/*
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* establish interrupt handler.
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* level is very high to allow high priority sub-interrupts.
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*/
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sc->sc_ipl = IPL_AUDIO;
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sc->sc_ih = pxa2x0_gpio_intr_establish(0, IST_EDGE_FALLING, sc->sc_ipl,
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obio_intr, sc);
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sc->sc_si = softint_establish(SOFTINT_NET, obio_softint, sc);
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reg = bus_space_read_2(iot, sc->sc_obioreg_ioh, G42XXEB_PLDVER);
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aprint_normal(": board %d version %x\n", reg>>8, reg & 0xff);
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/*
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* Attach each devices
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*/
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config_search_ia(obio_search, self, "obio", NULL);
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return;
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fail:
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aprint_error_dev(self, "can't map FPGA registers\n");
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}
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int
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obio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
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{
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struct obio_softc *sc = device_private(parent);
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struct obio_attach_args oba;
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oba.oba_sc = sc;
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oba.oba_iot = sc->sc_iot;
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oba.oba_addr = cf->cf_loc[OBIOCF_ADDR];
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oba.oba_intr = cf->cf_loc[OBIOCF_INTR];
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if (config_match(parent, cf, &oba) > 0)
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config_attach(parent, cf, &oba, obio_print);
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return 0;
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}
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void *
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obio_intr_establish(struct obio_softc *sc, int irq, int ipl,
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int type, int (*func)(void *), void *arg)
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{
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int save;
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int regidx, sft;
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uint16_t reg;
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static const uint8_t ist_code[] = {
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0,
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G42XXEB_INT_EDGE_FALLING, /* pulse */
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G42XXEB_INT_EDGE_FALLING, /* IST_EDGE */
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G42XXEB_INT_LEVEL_LOW, /* IST_LEVEL */
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G42XXEB_INT_LEVEL_HIGH, /* IST_LEVEL_HIGH */
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G42XXEB_INT_EDGE_RISING, /* IST_EDGE_RISING */
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G42XXEB_INT_EDGE_BOTH, /* IST_EDGE_BOTH */
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};
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if (irq < 0 || G42XXEB_N_INTS <= irq)
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panic("Bad irq no. for obio (%d)", irq);
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if (type < 0 || IST_EDGE_BOTH < type)
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panic("Bad interrupt type for obio (%d)", type);
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regidx = G42XXEB_INTCNTL;
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sft = 3 * irq;
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if (irq >= 5) {
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regidx = G42XXEB_INTCNTH;
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sft -= 3*5;
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}
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save = disable_interrupts(I32_bit);
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sc->sc_handler[irq].func = func;
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sc->sc_handler[irq].arg = arg;
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sc->sc_handler[irq].level = ipl;
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/* set interrupt type */
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reg = bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, regidx);
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bus_space_write_2(sc->sc_iot, sc->sc_obioreg_ioh, regidx,
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(reg & ~(7<<sft)) | (ist_code[type] << sft));
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#ifdef DEBUG
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printf("INTCTL=%x,%x\n",
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bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTCNTL),
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bus_space_read_2(sc->sc_iot, sc->sc_obioreg_ioh, G42XXEB_INTCNTH));
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#endif
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sc->sc_intr_mask &= ~(1U << irq);
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obio_update_intrmask(sc);
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restore_interrupts(save);
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#if 0
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if (ipl > sc->sc_ipl) {
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pxa2x0_update_intr_masks(sc->sc_intr, ipl);
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sc->sc_ipl = ipl;
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}
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#endif
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return &sc->sc_handler[irq];
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}
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void
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obio_intr_disestablish(struct obio_softc *sc, int irq, int (* func)(void *))
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{
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int error = 0;
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int save;
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save = disable_interrupts(I32_bit);
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if (sc->sc_handler[irq].func != func)
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error = 1;
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else {
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sc->sc_handler[irq].func = obio_spurious;
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sc->sc_handler[irq].level = IPL_NONE;
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sc->sc_intr_pending &= ~(1U << irq);
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sc->sc_intr_mask |= (1U << irq);
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obio_update_intrmask(sc);
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}
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restore_interrupts(save);
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if (error)
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aprint_error_dev(sc->sc_dev, "bad intr_disestablish\n");
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}
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void
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obio_intr_mask(struct obio_softc *sc, struct obio_handler *ih)
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{
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int irqno;
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int save;
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irqno = ih - sc->sc_handler;
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#ifdef DIAGNOSTIC
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if (ih == NULL || ih->func==NULL || irqno < 0 ||
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irqno >= G42XXEB_N_INTS)
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panic("Bad arg for obio_intr_mask");
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#endif
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save = disable_interrupts(I32_bit);
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sc->sc_intr_mask |= 1U<<irqno;
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obio_update_intrmask(sc);
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restore_interrupts(save);
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}
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void
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obio_intr_unmask(struct obio_softc *sc, struct obio_handler *ih)
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{
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int irqno;
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int save;
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irqno = ih - sc->sc_handler;
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#ifdef DIAGNOSTIC
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if (ih == NULL || ih->func==NULL || irqno < 0 ||
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irqno >= G42XXEB_N_INTS)
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panic("Bad arg for obio_intr_unmask");
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#endif
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save = disable_interrupts(I32_bit);
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sc->sc_intr_mask &= ~(1U<<irqno);
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obio_update_intrmask(sc);
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restore_interrupts(save);
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}
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void
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obio_peripheral_reset(struct obio_softc *bsc, int no, int onoff)
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{
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uint16_t reg;
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reg = bus_space_read_2(bsc->sc_iot, bsc->sc_obioreg_ioh,
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G42XXEB_RST);
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bus_space_write_2(bsc->sc_iot, bsc->sc_obioreg_ioh, G42XXEB_RST,
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onoff ? (reg & ~RST_EXT(no)) : (reg | RST_EXT(no)));
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}
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