841 lines
18 KiB
C
841 lines
18 KiB
C
/* $NetBSD: footbridge_com.c,v 1.7 2001/05/02 10:32:13 scw Exp $ */
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/*-
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* Copyright (c) 1997 Mark Brinicombe
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* Copyright (c) 1997 Causality Limited
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* COM driver, using the footbridge UART
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*/
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ioctl.h>
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#include <sys/select.h>
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#include <sys/tty.h>
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#include <sys/proc.h>
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#include <sys/conf.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/termios.h>
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#include <machine/bus.h>
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#include <machine/irqhandler.h>
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#include <arm32/footbridge/dc21285mem.h>
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#include <arm32/footbridge/dc21285reg.h>
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#include <arm32/footbridge/footbridgevar.h>
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#include <dev/cons.h>
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#include "fcom.h"
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extern u_int dc21285_fclk;
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#ifdef DDB
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/*
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* Define the keycode recognised as a request to call the debugger
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* A value of 0 disables the feature when DDB is built in
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*/
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#ifndef DDB_KEYCODE
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#define DDB_KEYCODE 0
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#endif /* DDB_KEYCODE */
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#endif /* DDB */
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struct fcom_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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void *sc_ih;
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struct callout sc_softintr_ch;
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int sc_rx_irq;
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int sc_tx_irq;
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int sc_hwflags;
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#define HW_FLAG_CONSOLE 0x01
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int sc_swflags;
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int sc_l_ubrlcr;
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int sc_m_ubrlcr;
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int sc_h_ubrlcr;
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char *sc_rxbuffer[2];
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char *sc_rxbuf;
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int sc_rxpos;
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int sc_rxcur;
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struct tty *sc_tty;
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};
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#define RX_BUFFER_SIZE 0x100
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/* Macros to clear/set/test flags. */
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#define SET(t, f) (t) |= (f)
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#define CLR(t, f) (t) &= ~(f)
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#define ISSET(t, f) ((t) & (f))
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static int fcom_probe __P((struct device *, struct cfdata *, void *));
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static void fcom_attach __P((struct device *, struct device *, void *));
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int fcomopen __P((dev_t dev, int flag, int mode, struct proc *p));
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static int fcom_rxintr __P((void *));
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/*static int fcom_txintr __P((void *));*/
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/*struct consdev;*/
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/*void fcomcnprobe __P((struct consdev *));
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void fcomcninit __P((struct consdev *));*/
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int fcomcngetc __P((dev_t));
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void fcomcnputc __P((dev_t, int));
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void fcomcnpollc __P((dev_t, int));
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struct cfattach fcom_ca = {
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sizeof(struct fcom_softc), fcom_probe, fcom_attach
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};
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extern struct cfdriver fcom_cd;
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void fcominit __P((bus_space_tag_t, bus_space_handle_t, int, int));
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void fcominitcons __P((bus_space_tag_t, bus_space_handle_t));
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bus_space_tag_t fcomconstag;
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bus_space_handle_t fcomconsioh;
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extern int comcnmode;
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extern int comcnspeed;
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#define COMUNIT(x) (minor(x))
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#ifndef CONUNIT
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#define CONUNIT 0
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#endif
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/*
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* The console is set up at init time, well in advance of the reset of the
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* system and thus we have a private bus space tag for the console.
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*
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* The tag is provided by fcom_io.c and fcom_io_asm.S
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*/
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extern struct bus_space fcomcons_bs_tag;
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/*
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* int fcom_probe(struct device *parent, struct cfdata *cf, void *aux)
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*
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* Make sure we are trying to attach a com device and then
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* probe for one.
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*/
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static int
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fcom_probe(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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union footbridge_attach_args *fba = aux;
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if (strcmp(fba->fba_name, "fcom") == 0)
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return(1);
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return(0);
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}
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/*
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* void fcom_attach(struct device *parent, struct device *self, void *aux)
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*
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* attach the com device
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*/
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static void
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fcom_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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union footbridge_attach_args *fba = aux;
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struct fcom_softc *sc = (struct fcom_softc *)self;
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/* Set up the softc */
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sc->sc_iot = fba->fba_fca.fca_iot;
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sc->sc_ioh = fba->fba_fca.fca_ioh;
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callout_init(&sc->sc_softintr_ch);
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sc->sc_rx_irq = fba->fba_fca.fca_rx_irq;
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sc->sc_tx_irq = fba->fba_fca.fca_tx_irq;
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sc->sc_hwflags = 0;
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sc->sc_swflags = 0;
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/* If we have a console tag then make a note of it */
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if (fcomconstag)
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sc->sc_hwflags |= HW_FLAG_CONSOLE;
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if (sc->sc_hwflags & HW_FLAG_CONSOLE) {
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int major;
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/* locate the major number */
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for (major = 0; major < nchrdev; ++major)
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if (cdevsw[major].d_open == fcomopen)
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break;
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cn_tab->cn_dev = makedev(major, sc->sc_dev.dv_unit);
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printf(": console");
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}
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printf("\n");
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sc->sc_ih = intr_claim(sc->sc_rx_irq, IPL_SERIAL, "serial rx",
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fcom_rxintr, sc);
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if (sc->sc_ih == NULL)
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panic("%s: Cannot install rx interrupt handler\n",
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sc->sc_dev.dv_xname);
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}
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static void fcomstart __P((struct tty *));
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static int fcomparam __P((struct tty *, struct termios *));
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int
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fcomopen(dev, flag, mode, p)
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dev_t dev;
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int flag, mode;
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struct proc *p;
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{
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struct fcom_softc *sc;
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int unit = minor(dev);
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struct tty *tp;
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if (unit >= fcom_cd.cd_ndevs)
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return ENXIO;
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sc = fcom_cd.cd_devs[unit];
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if (!sc)
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return ENXIO;
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if (!(tp = sc->sc_tty))
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sc->sc_tty = tp = ttymalloc();
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if (!sc->sc_rxbuffer[0]) {
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sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK);
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sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK);
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sc->sc_rxpos = 0;
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sc->sc_rxcur = 0;
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sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur];
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if (!sc->sc_rxbuf)
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panic("%s: Cannot allocate rx buffer memory",
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sc->sc_dev.dv_xname);
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}
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tp->t_oproc = fcomstart;
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tp->t_param = fcomparam;
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tp->t_dev = dev;
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if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) {
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ttychars(tp);
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tp->t_cflag = TTYDEF_CFLAG;
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tp->t_iflag = TTYDEF_IFLAG;
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tp->t_oflag = TTYDEF_OFLAG;
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tp->t_lflag = TTYDEF_LFLAG;
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/*
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* Initialize the termios status to the defaults. Add in the
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* sticky bits from TIOCSFLAGS.
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*/
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tp->t_ispeed = 0;
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if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE))
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tp->t_ospeed = comcnspeed;
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else
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tp->t_ospeed = TTYDEF_SPEED;
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fcomparam(tp, &tp->t_termios);
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ttsetwater(tp);
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} else if ((tp->t_state&TS_XCLUDE) && suser(p->p_ucred, &p->p_acflag))
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return EBUSY;
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tp->t_state |= TS_CARR_ON;
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return (*tp->t_linesw->l_open)(dev, tp);
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}
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int
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fcomclose(dev, flag, mode, p)
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dev_t dev;
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int flag, mode;
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struct proc *p;
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{
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struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
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struct tty *tp = sc->sc_tty;
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/* XXX This is for cons.c. */
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if (!ISSET(tp->t_state, TS_ISOPEN))
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return (0);
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(*tp->t_linesw->l_close)(tp, flag);
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ttyclose(tp);
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#ifdef DIAGNOSTIC
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if (sc->sc_rxbuffer[0] == NULL)
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panic("fcomclose: rx buffers not allocated\n");
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#endif /* DIAGNOSTIC */
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free(sc->sc_rxbuffer[0], M_DEVBUF);
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free(sc->sc_rxbuffer[1], M_DEVBUF);
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sc->sc_rxbuffer[0] = NULL;
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sc->sc_rxbuffer[1] = NULL;
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return 0;
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}
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int
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fcomread(dev, uio, flag)
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dev_t dev;
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struct uio *uio;
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int flag;
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{
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struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
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struct tty *tp = sc->sc_tty;
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return (*tp->t_linesw->l_read)(tp, uio, flag);
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}
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int
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fcomwrite(dev, uio, flag)
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dev_t dev;
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struct uio *uio;
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int flag;
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{
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struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
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struct tty *tp = sc->sc_tty;
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return (*tp->t_linesw->l_write)(tp, uio, flag);
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}
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int
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fcompoll(dev, events, p)
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dev_t dev;
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int events;
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struct proc *p;
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{
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struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
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struct tty *tp = sc->sc_tty;
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return ((*tp->t_linesw->l_poll)(tp, events, p));
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}
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int
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fcomioctl(dev, cmd, data, flag, p)
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dev_t dev;
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u_long cmd;
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caddr_t data;
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int flag;
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struct proc *p;
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{
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struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
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struct tty *tp = sc->sc_tty;
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int error;
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if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p)) >= 0)
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return error;
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if ((error = ttioctl(tp, cmd, data, flag, p)) >= 0)
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return error;
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switch (cmd) {
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case TIOCGFLAGS:
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*(int *)data = sc->sc_swflags;
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break;
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case TIOCSFLAGS:
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error = suser(p->p_ucred, &p->p_acflag);
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if (error)
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return (error);
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sc->sc_swflags = *(int *)data;
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break;
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}
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return ENOTTY;
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}
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struct tty *
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fcomtty(dev)
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dev_t dev;
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{
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struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
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return sc->sc_tty;
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}
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void
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fcomstop(tp, flag)
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struct tty *tp;
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int flag;
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{
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}
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static void
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fcomstart(tp)
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struct tty *tp;
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{
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struct clist *cl;
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int s, len;
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u_char buf[64];
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int loop;
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struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)];
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int timo;
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s = spltty();
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if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) {
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(void)splx(s);
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return;
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}
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tp->t_state |= TS_BUSY;
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(void)splx(s);
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/* s = splserial();*/
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/* wait for any pending transmission to finish */
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timo = 100000;
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while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
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;
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s = splserial();
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if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) {
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tp->t_state |= TS_TIMEOUT;
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callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp);
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(void)splx(s);
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return;
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}
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(void)splx(s);
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cl = &tp->t_outq;
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len = q_to_b(cl, buf, 64);
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for (loop = 0; loop < len; ++loop) {
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/* s = splserial();*/
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bus_space_write_4(iot, ioh, UART_DATA, buf[loop]);
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/* wait for this transmission to complete */
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timo = 100000;
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while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
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;
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/* (void)splx(s);*/
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}
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s = spltty();
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tp->t_state &= ~TS_BUSY;
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if (cl->c_cc) {
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tp->t_state |= TS_TIMEOUT;
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callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp);
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}
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if (cl->c_cc <= tp->t_lowat) {
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if (tp->t_state & TS_ASLEEP) {
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tp->t_state &= ~TS_ASLEEP;
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wakeup(cl);
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}
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selwakeup(&tp->t_wsel);
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}
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(void)splx(s);
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}
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static int
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fcomparam(tp, t)
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struct tty *tp;
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struct termios *t;
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{
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struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)];
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int baudrate;
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int h_ubrlcr;
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int m_ubrlcr;
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int l_ubrlcr;
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int s;
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/* check requested parameters */
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if (t->c_ospeed < 0)
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return (EINVAL);
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if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
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return (EINVAL);
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switch (t->c_ospeed) {
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case B1200:
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case B2400:
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case B4800:
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case B9600:
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case B19200:
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case B38400:
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baudrate = UART_BRD(dc21285_fclk, t->c_ospeed);
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break;
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default:
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baudrate = UART_BRD(dc21285_fclk, 9600);
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break;
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}
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l_ubrlcr = baudrate & 0xff;
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m_ubrlcr = (baudrate >> 8) & 0xf;
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h_ubrlcr = 0;
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switch (ISSET(t->c_cflag, CSIZE)) {
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case CS5:
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h_ubrlcr |= UART_DATA_BITS_5;
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break;
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case CS6:
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h_ubrlcr |= UART_DATA_BITS_6;
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break;
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case CS7:
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h_ubrlcr |= UART_DATA_BITS_7;
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break;
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case CS8:
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h_ubrlcr |= UART_DATA_BITS_8;
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break;
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}
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if (ISSET(t->c_cflag, PARENB)) {
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h_ubrlcr |= UART_PARITY_ENABLE;
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if (ISSET(t->c_cflag, PARODD))
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h_ubrlcr |= UART_ODD_PARITY;
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else
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h_ubrlcr |= UART_EVEN_PARITY;
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}
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if (ISSET(t->c_cflag, CSTOPB))
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h_ubrlcr |= UART_STOP_BITS_2;
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bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
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bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
|
|
bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
|
|
|
|
s = splserial();
|
|
|
|
sc->sc_l_ubrlcr = l_ubrlcr;
|
|
sc->sc_m_ubrlcr = m_ubrlcr;
|
|
sc->sc_h_ubrlcr = h_ubrlcr;
|
|
|
|
/*
|
|
* For the console, always force CLOCAL and !HUPCL, so that the port
|
|
* is always active.
|
|
*/
|
|
if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
|
|
ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) {
|
|
SET(t->c_cflag, CLOCAL);
|
|
CLR(t->c_cflag, HUPCL);
|
|
}
|
|
|
|
/* and copy to tty */
|
|
tp->t_ispeed = 0;
|
|
tp->t_ospeed = t->c_ospeed;
|
|
tp->t_cflag = t->c_cflag;
|
|
|
|
bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
|
|
bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
|
|
bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
|
|
|
|
(void)splx(s);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int softint_scheduled = 0;
|
|
|
|
static void
|
|
fcom_softintr(sc)
|
|
struct fcom_softc *sc;
|
|
{
|
|
struct tty *tp = sc->sc_tty;
|
|
int s;
|
|
int loop;
|
|
int len;
|
|
char *ptr;
|
|
|
|
s = spltty();
|
|
ptr = sc->sc_rxbuf;
|
|
len = sc->sc_rxpos;
|
|
sc->sc_rxcur ^= 1;
|
|
sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur];
|
|
sc->sc_rxpos = 0;
|
|
(void)splx(s);
|
|
|
|
for (loop = 0; loop < len; ++loop)
|
|
(*tp->t_linesw->l_rint)(ptr[loop], tp);
|
|
softint_scheduled = 0;
|
|
}
|
|
|
|
#if 0
|
|
static int
|
|
fcom_txintr(arg)
|
|
void *arg;
|
|
{
|
|
/* struct fcom_softc *sc = arg;*/
|
|
|
|
printf("fcom_txintr()\n");
|
|
return(0);
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
fcom_rxintr(arg)
|
|
void *arg;
|
|
{
|
|
struct fcom_softc *sc = arg;
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
|
struct tty *tp = sc->sc_tty;
|
|
int status;
|
|
int byte;
|
|
|
|
do {
|
|
status = bus_space_read_4(iot, ioh, UART_FLAGS);
|
|
if ((status & UART_RX_FULL))
|
|
break;
|
|
byte = bus_space_read_4(iot, ioh, UART_DATA);
|
|
status = bus_space_read_4(iot, ioh, UART_RX_STAT);
|
|
#if DDB_KEYCODE > 0
|
|
/*
|
|
* Temporary hack so that I can force the kernel into
|
|
* the debugger via the serial port
|
|
*/
|
|
if (byte == DDB_KEYCODE) Debugger();
|
|
#endif
|
|
if (tp && (tp->t_state & TS_ISOPEN))
|
|
if (sc->sc_rxpos < RX_BUFFER_SIZE) {
|
|
sc->sc_rxbuf[sc->sc_rxpos++] = byte;
|
|
if (!softint_scheduled) {
|
|
softint_scheduled = 1;
|
|
callout_reset(&sc->sc_softintr_ch,
|
|
1, fcom_softintr, sc);
|
|
}
|
|
}
|
|
} while (1);
|
|
return(0);
|
|
}
|
|
|
|
#if 0
|
|
void
|
|
fcom_iflush(sc)
|
|
struct fcom_softc *sc;
|
|
{
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
|
|
|
/* flush any pending I/O */
|
|
while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL))
|
|
(void) bus_space_read_4(iot, ioh, UART_DATA);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Following are all routines needed for COM to act as console
|
|
*/
|
|
|
|
#if 0
|
|
void
|
|
fcomcnprobe(cp)
|
|
struct consdev *cp;
|
|
{
|
|
int major;
|
|
|
|
/* Serial console is always present so no probe */
|
|
|
|
/* locate the major number */
|
|
for (major = 0; major < nchrdev; major++)
|
|
if (cdevsw[major].d_open == fcomopen)
|
|
break;
|
|
|
|
/* initialize required fields */
|
|
cp->cn_dev = makedev(major, CONUNIT);
|
|
cp->cn_pri = CN_REMOTE; /* Force a serial port console */
|
|
}
|
|
|
|
void
|
|
fcomcninit(cp)
|
|
struct consdev *cp;
|
|
{
|
|
fcomconstag = &fcomcons_bs_tag;
|
|
|
|
if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh))
|
|
panic("fcomcninit: mapping failed");
|
|
|
|
fcominitcons(fcomconstag, fcomconsioh);
|
|
}
|
|
#endif
|
|
|
|
int
|
|
fcomcnattach(iobase, rate, cflag)
|
|
u_int iobase;
|
|
int rate;
|
|
tcflag_t cflag;
|
|
{
|
|
static struct consdev fcomcons = {
|
|
NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL,
|
|
NODEV, CN_NORMAL
|
|
};
|
|
|
|
fcomconstag = &fcomcons_bs_tag;
|
|
|
|
if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE,
|
|
0, &fcomconsioh))
|
|
panic("fcomcninit: mapping failed");
|
|
|
|
fcominit(fcomconstag, fcomconsioh, rate, cflag);
|
|
|
|
cn_tab = &fcomcons;
|
|
|
|
/* comcnspeed = rate;
|
|
comcnmode = cflag;*/
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
fcomcndetach(void)
|
|
{
|
|
bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE);
|
|
|
|
cn_tab = NULL;
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Initialize UART to known state.
|
|
*/
|
|
void
|
|
fcominit(iot, ioh, rate, mode)
|
|
bus_space_tag_t iot;
|
|
bus_space_handle_t ioh;
|
|
int rate;
|
|
int mode;
|
|
{
|
|
int baudrate;
|
|
int h_ubrlcr;
|
|
int m_ubrlcr;
|
|
int l_ubrlcr;
|
|
|
|
switch (rate) {
|
|
case B1200:
|
|
case B2400:
|
|
case B4800:
|
|
case B9600:
|
|
case B19200:
|
|
case B38400:
|
|
baudrate = UART_BRD(dc21285_fclk, rate);
|
|
break;
|
|
default:
|
|
baudrate = UART_BRD(dc21285_fclk, 9600);
|
|
break;
|
|
}
|
|
|
|
h_ubrlcr = 0;
|
|
switch (mode & CSIZE) {
|
|
case CS5:
|
|
h_ubrlcr |= UART_DATA_BITS_5;
|
|
break;
|
|
case CS6:
|
|
h_ubrlcr |= UART_DATA_BITS_6;
|
|
break;
|
|
case CS7:
|
|
h_ubrlcr |= UART_DATA_BITS_7;
|
|
break;
|
|
case CS8:
|
|
h_ubrlcr |= UART_DATA_BITS_8;
|
|
break;
|
|
}
|
|
|
|
if (mode & PARENB)
|
|
h_ubrlcr |= UART_PARITY_ENABLE;
|
|
if (mode & PARODD)
|
|
h_ubrlcr |= UART_ODD_PARITY;
|
|
else
|
|
h_ubrlcr |= UART_EVEN_PARITY;
|
|
|
|
if (mode & CSTOPB)
|
|
h_ubrlcr |= UART_STOP_BITS_2;
|
|
|
|
m_ubrlcr = (baudrate >> 8) & 0xf;
|
|
l_ubrlcr = baudrate & 0xff;
|
|
|
|
bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
|
|
bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
|
|
bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
|
|
}
|
|
#if 0
|
|
/*
|
|
* Set UART for console use. Do normal init, then enable interrupts.
|
|
*/
|
|
void
|
|
fcominitcons(iot, ioh)
|
|
bus_space_tag_t iot;
|
|
bus_space_handle_t ioh;
|
|
{
|
|
int s = splserial();
|
|
|
|
fcominit(iot, ioh, comcnspeed, comcnmode);
|
|
|
|
delay(10000);
|
|
|
|
(void)splx(s);
|
|
}
|
|
#endif
|
|
|
|
int
|
|
fcomcngetc(dev)
|
|
dev_t dev;
|
|
{
|
|
int s = splserial();
|
|
bus_space_tag_t iot = fcomconstag;
|
|
bus_space_handle_t ioh = fcomconsioh;
|
|
u_char stat, c;
|
|
|
|
while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0)
|
|
;
|
|
c = bus_space_read_4(iot, ioh, UART_DATA);
|
|
stat = bus_space_read_4(iot, ioh, UART_RX_STAT);
|
|
(void)splx(s);
|
|
#if DDB_KEYCODE > 0
|
|
/*
|
|
* Temporary hack so that I can force the kernel into
|
|
* the debugger via the serial port
|
|
*/
|
|
if (c == DDB_KEYCODE) Debugger();
|
|
#endif
|
|
|
|
return (c);
|
|
}
|
|
|
|
/*
|
|
* Console kernel output character routine.
|
|
*/
|
|
void
|
|
fcomcnputc(dev, c)
|
|
dev_t dev;
|
|
int c;
|
|
{
|
|
int s = splserial();
|
|
bus_space_tag_t iot = fcomconstag;
|
|
bus_space_handle_t ioh = fcomconsioh;
|
|
int timo;
|
|
|
|
/* wait for any pending transmission to finish */
|
|
timo = 50000;
|
|
while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
|
|
;
|
|
bus_space_write_4(iot, ioh, UART_DATA, c);
|
|
|
|
/* wait for this transmission to complete */
|
|
timo = 1500000;
|
|
while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
|
|
;
|
|
/* Clear interrupt status here */
|
|
(void)splx(s);
|
|
}
|
|
|
|
void
|
|
fcomcnpollc(dev, on)
|
|
dev_t dev;
|
|
int on;
|
|
{
|
|
}
|