937a7a3ed9
This is a completely rewritten scsipi_xfer execution engine, and the associated changes to HBA drivers. Overview of changes & features: - All xfers are queued in the mid-layer, rather than doing so in an ad-hoc fashion in individual adapter drivers. - Adapter/channel resource management in the mid-layer, avoids even trying to start running an xfer if the adapter/channel doesn't have the resources. - Better communication between the mid-layer and the adapters. - Asynchronous event notification mechanism from adapter to mid-layer and peripherals. - Better peripheral queue management: freeze/thaw, sorted requeueing during recovery, etc. - Clean separation of peripherals, adapters, and adapter channels (no more scsipi_link). - Kernel thread for each scsipi_channel makes error recovery much easier (no more dealing with interrupt context when recovering from an error). - Mid-layer support for tagged queueing: commands can have the tag type set explicitly, tag IDs are allocated in the mid-layer (thus eliminating the need to use buggy tag ID allocation schemes in many adapter drivers). - support for QUEUE FULL and CHECK CONDITION status in mid-layer; the command will be requeued, or a REQUEST SENSE will be sent as appropriate. Just before the merge syssrc has been tagged with thorpej_scsipi_beforemerge
298 lines
8.1 KiB
C
298 lines
8.1 KiB
C
/* $NetBSD: dpt_isa.c,v 1.5 2001/04/25 17:53:35 bouyer Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Andrew Doran <ad@netbsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* ISA front-end for DPT EATA SCSI driver.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/queue.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <dev/isa/isadmareg.h>
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#include <dev/isa/isadmavar.h>
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#include <dev/ic/dptreg.h>
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#include <dev/ic/dptvar.h>
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#define DPT_ISA_IOSIZE 16
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#define DPT_ISA_MAXCCBS 16
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static void dpt_isa_attach(struct device *, struct device *, void *);
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static int dpt_isa_match(struct device *, struct cfdata *, void *);
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static int dpt_isa_probe(struct isa_attach_args *, int);
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static int dpt_isa_wait(bus_space_handle_t, bus_space_tag_t, u_int8_t,
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u_int8_t);
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struct cfattach dpt_isa_ca = {
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sizeof(struct dpt_softc), dpt_isa_match, dpt_isa_attach
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};
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/* Try 'less intrusive' addresses first */
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static const int dpt_isa_iobases[] = { 0x230, 0x330, 0x1f0, 0x170, 0 };
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/*
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* Wait for the HBA status register to reach a specific state.
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*/
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static int
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dpt_isa_wait(bus_space_handle_t ioh, bus_space_tag_t iot, u_int8_t mask,
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u_int8_t state)
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{
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int ms;
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for (ms = 2000 * 10; ms; ms--) {
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if ((bus_space_read_1(iot, ioh, HA_STATUS) & mask) == state)
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return (0);
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DELAY(100);
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}
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return (-1);
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}
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/*
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* Match a supported board.
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*/
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static int
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dpt_isa_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct isa_attach_args *ia;
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int i;
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ia = aux;
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if (ia->ia_iobase != ISACF_PORT_DEFAULT)
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return (dpt_isa_probe(ia, ia->ia_iobase));
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for (i = 0; dpt_isa_iobases[i] != 0; i++)
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if (dpt_isa_probe(ia, dpt_isa_iobases[i])) {
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ia->ia_iobase = dpt_isa_iobases[i];
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return (1);
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}
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return (0);
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}
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/*
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* Probe for a supported board.
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*/
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static int
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dpt_isa_probe(struct isa_attach_args *ia, int iobase)
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{
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struct eata_cfg ec;
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bus_space_handle_t ioh;
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bus_space_tag_t iot;
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int i, j, stat;
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u_int16_t *p;
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iot = ia->ia_iot;
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if (bus_space_map(iot, iobase, DPT_ISA_IOSIZE, 0, &ioh) != 0)
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return(0);
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/*
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* Assumuing the DPT BIOS reset the board, we shouldn't need to
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* re-do it here. The tests below should weed out non-EATA devices
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* before we start poking any registers.
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*/
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for (i = 1000; i; i--) {
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if ((bus_space_read_1(iot, ioh, HA_STATUS) & HA_ST_READY) != 0)
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break;
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DELAY(2000);
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}
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if (i == 0)
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goto bad;
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while((((stat = bus_space_read_1(iot, ioh, HA_STATUS))
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!= (HA_ST_READY|HA_ST_SEEK_COMPLETE))
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&& (stat != (HA_ST_READY|HA_ST_SEEK_COMPLETE|HA_ST_ERROR))
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&& (stat != (HA_ST_READY|HA_ST_SEEK_COMPLETE|HA_ST_ERROR|HA_ST_DRQ)))
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|| (dpt_isa_wait(ioh, iot, HA_ST_BUSY, 0)))
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/* RAID drives still spinning up? */
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if (bus_space_read_1(iot, ioh, HA_ERROR) != 'D' ||
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bus_space_read_1(iot, ioh, HA_ERROR + 1) != 'P' ||
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bus_space_read_1(iot, ioh, HA_ERROR + 2) != 'T')
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goto bad;
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/*
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* At this point we can be confident that we are dealing with a DPT
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* HBA. Issue the read-config command and wait for the data to
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* appear. XXX We shouldn't be doing this with PIO, but it makes it
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* a lot easier as no DMA setup is required.
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*/
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bus_space_write_1(iot, ioh, HA_COMMAND, CP_PIO_GETCFG);
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memset(&ec, 0, sizeof(ec));
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i = ((int)&((struct eata_cfg *)0)->ec_cfglen +
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sizeof(ec.ec_cfglen)) >> 1;
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p = (u_int16_t *)&ec;
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if (dpt_isa_wait(ioh, iot, 0xFF, HA_ST_DATA_RDY))
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goto bad;
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/* Begin reading */
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while (i--)
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*p++ = bus_space_read_stream_2(iot, ioh, HA_DATA);
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if ((i = ec.ec_cfglen) > (sizeof(struct eata_cfg)
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- (int)(&(((struct eata_cfg *)0L)->ec_cfglen))
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- sizeof(ec.ec_cfglen)))
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i = sizeof(struct eata_cfg)
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- (int)(&(((struct eata_cfg *)0L)->ec_cfglen))
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- sizeof(ec.ec_cfglen);
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j = i + (int)(&(((struct eata_cfg *)0L)->ec_cfglen)) +
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sizeof(ec.ec_cfglen);
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i >>= 1;
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while (i--)
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*p++ = bus_space_read_stream_2(iot, ioh, HA_DATA);
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/* Flush until we have read 512 bytes. */
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i = (512 - j + 1) >> 1;
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while (i--)
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bus_space_read_stream_2(iot, ioh, HA_DATA);
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/* Puke if we don't like the returned configuration data. */
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if ((bus_space_read_1(iot, ioh, HA_STATUS) & HA_ST_ERROR) != 0 ||
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memcmp(ec.ec_eatasig, "EATA", 4) != 0 ||
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(ec.ec_feat0 & (EC_F0_HBA_VALID | EC_F0_DMA_SUPPORTED)) !=
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(EC_F0_HBA_VALID | EC_F0_DMA_SUPPORTED))
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goto bad;
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/*
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* Which DMA channel to use: if it was hardwired in the kernel
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* configuration, use that value. If the HBA told us, use that
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* value. Otherwise, puke.
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*/
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if (ia->ia_drq == -1) {
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int dmanum = ((ec.ec_feat1 & EC_F1_DMA_NUM_MASK) >>
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EC_F1_DMA_NUM_SHIFT);
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if ((ec.ec_feat0 & EC_F0_DMA_NUM_VALID) == 0 || dmanum > 3)
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goto bad;
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ia->ia_drq = "\0\7\6\5"[dmanum];
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}
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/*
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* Which IRQ to use: if it was hardwired in the kernel configuration,
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* use that value. Otherwise, use what the HBA told us.
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*/
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if (ia->ia_irq == -1)
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ia->ia_irq = ((ec.ec_feat1 & EC_F1_IRQ_NUM_MASK) >>
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EC_F1_IRQ_NUM_SHIFT);
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ia->ia_msize = 0;
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ia->ia_iosize = DPT_ISA_IOSIZE;
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bus_space_unmap(iot, ioh, DPT_ISA_IOSIZE);
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return (1);
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bad:
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bus_space_unmap(iot, ioh, DPT_ISA_IOSIZE);
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return (0);
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}
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/*
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* Attach a matched board.
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*/
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static void
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dpt_isa_attach(struct device *parent, struct device *self, void *aux)
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{
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struct isa_attach_args *ia;
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isa_chipset_tag_t ic;
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bus_space_handle_t ioh;
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bus_space_tag_t iot;
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struct dpt_softc *sc;
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struct eata_cfg *ec;
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int error;
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ia = aux;
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sc = (struct dpt_softc *)self;
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iot = ia->ia_iot;
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ic = ia->ia_ic;
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printf(": ");
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if ((error = bus_space_map(iot, ia->ia_iobase, DPT_ISA_IOSIZE, 0,
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&ioh)) != 0) {
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printf("can't map i/o space, error = %d\n", error);
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return;
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}
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sc->sc_iot = iot;
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sc->sc_ioh = ioh;
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sc->sc_dmat = ia->ia_dmat;
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if ((error = isa_dmacascade(ic, ia->ia_drq)) != 0) {
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printf("unable to cascade DRQ, error = %d\n", error);
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return;
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}
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/* Establish the interrupt. */
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sc->sc_ih = isa_intr_establish(ic, ia->ia_irq, IST_EDGE, IPL_BIO,
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dpt_intr, sc);
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if (sc->sc_ih == NULL) {
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printf("can't establish interrupt\n");
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return;
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}
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if (dpt_readcfg(sc)) {
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printf("readcfg failed - see dpt(4)\n");
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return;
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}
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/*
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* Now attach to the bus-independent code. XXX We need to force
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* parameters that aren't filled in by some ISA boards. In
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* particular, due to the limited amount of memory we have to play
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* with for DMA, clamp the number of CCBs to 16.
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*/
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ec = &sc->sc_ec;
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if (be16toh(*(int16_t *)ec->ec_queuedepth) > DPT_ISA_MAXCCBS)
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*(int16_t *)ec->ec_queuedepth = htobe16(DPT_ISA_MAXCCBS);
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if (ec->ec_maxlun == 0)
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ec->ec_maxlun = 7;
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if ((ec->ec_feat3 & EC_F3_MAX_TARGET_MASK) >> EC_F3_MAX_TARGET_SHIFT
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== 0)
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ec->ec_feat3 = (ec->ec_feat3 & ~EC_F3_MAX_TARGET_MASK) |
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(7 << EC_F3_MAX_TARGET_SHIFT);
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/* Now attach to the bus-independent code. */
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dpt_init(sc, NULL);
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}
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