191 lines
5.8 KiB
C
191 lines
5.8 KiB
C
/* $NetBSD: igsfbreg.h,v 1.1 2002/03/30 19:48:56 uwe Exp $ */
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/*
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* Copyright (c) 2002 Valeriy E. Ushakov
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Integraphics Systems IGA 1682 and (untested) CyberPro 2k.
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*/
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#ifndef _DEV_IC_IGSFBREG_H_
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#define _DEV_IC_IGSFBREG_H_
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/*
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* Magic address decoding for memory space accesses in CyberPro.
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*/
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#define IGS_MEM_MMIO_SELECT 0x00800000 /* memory mapped i/o */
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#define IGS_MEM_BE_SELECT 0x00400000 /* endian */
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/*
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* Registers in I/O space (could be memory-mapped i/o).
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*/
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#define IGS_IO_SIZE 0x400
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#define IGS_COP_SIZE 0x400
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/*
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* Cursor sprite data: 64x64 pixels, 2bpp = 1Kb.
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*/
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#define IGS_CURSOR_DATA_SIZE 0x0400
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/*
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* Starting up the chip.
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*/
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/* Video Enable/Setup */
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#define IGS_VDO 0x46e8
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#define IGS_VDO_ENABLE 0x08
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#define IGS_VDO_SETUP 0x10
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/* Video Enable */
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#define IGS_VSE 0x102
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#define IGS_VSE_ENABLE 0x01
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/*
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* Palette Read/Write: write palette index to the index port.
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* Read/write R/G/B in three consecutive accesses to data port.
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* After third access to data the index is autoincremented and you can
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* proceed with reading/writing data port for the next entry.
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*
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* When MRS2 bit in sprite control is set, these registers are used to
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* access sprite (i.e. cursor) 2-color palette. (NB: apparently, in
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* this mode index autoincrement doesn't work).
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*/
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#define IGS_DAC_PEL_READ_IDX 0x3c7
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#define IGS_DAC_PEL_WRITE_IDX 0x3c8
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#define IGS_DAC_PEL_DATA 0x3c9
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/*
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* Extended Registers. Indexed access via IGS_EXT_PORT.
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*/
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#define IGS_EXT_IDX 0x3ce
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/*
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* Sync Control.
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* Two bit combinations for h/v:
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* 00 - normal, 01 - force 0, 1x - force 1
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*/
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#define IGS_EXT_SYNC_CTL 0x16
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#define IGS_EXT_SYNC_H0 0x01
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#define IGS_EXT_SYNC_H1 0x02
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#define IGS_EXT_SYNC_V0 0x04
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#define IGS_EXT_SYNC_V1 0x08
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/*
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* For PCI just use normal BAR config.
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*/
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#define IGS_EXT_BUS_CTL 0x30
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#define IGS_EXT_BUS_CTL_LINSIZE_SHIFT 0
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#define IGS_EXT_BUS_CTL_LINSIZE_MASK 0x03
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#define IGS_EXT_BUS_CTL_LINSIZE(x) \
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(((x) >> IGS_EXT_BUS_CTL_LINSIZE_SHIFT) & IGS_EXT_BUS_CTL_LINSIZE_MASK)
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/*
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* COPREN - enable direct access to coprocessor registers
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* COPASELB - COP address select 0xbfc00..0xbffff
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*/
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#define IGS_EXT_BIU_MISC_CTL 0x33
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#define IGS_EXT_BIU_LINEAREN 0x01
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#define IGS_EXT_BIU_LIN2MEM 0x02
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#define IGS_EXT_BIU_COPREN 0x04
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#define IGS_EXT_BIU_COPASELB 0x08
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#define IGS_EXT_BIU_SEGON 0x10
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#define IGS_EXT_BIU_SEG2MEM 0x20
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/*
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* Linear Address register
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* PCI: don't write directly, just use nomral PCI configuration
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* ISA: only bits [23..20] are programmable, the rest MBZ
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*/
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#define IGS_EXT_LINA_LO 0x34 /* [3..0] -> [23..20] */
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#define IGS_EXT_LINA_HI 0x35 /* [7..0] -> [31..24] */
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/* Hardware cursor (sprite) */
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#define IGS_EXT_SPRITE_HSTART_LO 0x50
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#define IGS_EXT_SPRITE_HSTART_HI 0x51 /* bits [2..0] */
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#define IGS_EXT_SPRITE_HPRESET 0x52 /* bits [5..0] */
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#define IGS_EXT_SPRITE_VSTART_LO 0x53
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#define IGS_EXT_SPRITE_VSTART_HI 0x54 /* bits [2..0] */
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#define IGS_EXT_SPRITE_VPRESET 0x55 /* bits [5..0] */
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#define IGS_EXT_SPRITE_CTL 0x56
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#define IGS_EXT_SPRITE_VISIBLE 0x01
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#define IGS_EXT_SPRITE_64x64 0x02
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#define IGS_EXT_SPRITE_SELECT 0x04
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/* Overscan R/G/B registers */
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#define IGS_EXT_OVERSCAN_RED 0x58
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#define IGS_EXT_OVERSCAN_GREEN 0x59
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#define IGS_EXT_OVERSCAN_BLUE 0x5a
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/* Hardware cursor (sprite) data location */
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#define IGS_EXT_SPRITE_DATA_LO 0x7e
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#define IGS_EXT_SPRITE_DATA_HI 0x7f /* bits [3..0] */
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/*********************************************************************
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* Access sugar for indexed registers
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*/
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static __inline__ u_int8_t
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igs_idx_read(bus_space_tag_t, bus_space_handle_t, u_int, u_int8_t);
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static __inline__ u_int8_t
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igs_idx_read(t, h, idxport, idx)
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bus_space_tag_t t;
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bus_space_handle_t h;
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u_int idxport;
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u_int8_t idx;
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{
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bus_space_write_1(t, h, idxport, idx);
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return (bus_space_read_1(t, h, idxport + 1));
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}
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static __inline__ void
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igs_idx_write(bus_space_tag_t, bus_space_handle_t, u_int, u_int8_t, u_int8_t);
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static __inline__ void
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igs_idx_write(t, h, idxport, idx, val)
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bus_space_tag_t t;
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bus_space_handle_t h;
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u_int idxport;
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u_int8_t idx, val;
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{
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bus_space_write_1(t, h, idxport, idx);
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bus_space_write_1(t, h, idxport + 1, val);
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}
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/* more sugar for extended registers */
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#define igs_ext_read(t,h,x) (igs_idx_read((t),(h),IGS_EXT_IDX,(x)))
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#define igs_ext_write(t,h,x,v) (igs_idx_write((t),(h),IGS_EXT_IDX,(x),(v)))
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#endif /* _DEV_IC_IGSFBREG_H_ */
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