94 lines
4.5 KiB
C
94 lines
4.5 KiB
C
/* $NetBSD: tqphyreg.h,v 1.2 1999/09/16 05:58:18 soren Exp $ */
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/*
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* Copyright (c) 1999 Soren S. Jorvang.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DEV_MII_TQPHYREG_H_
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#define _DEV_MII_TQPHYREG_H_
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/*
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* TDK TSC78Q2120 PHY registers
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*
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* Documentation available at http://www.tsc.tdk.com/lan/78Q2120.pdf .
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*/
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/*
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* http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html has this to say:
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*
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* TDK Semiconductor (formerly Silicon Systems) 78Q2120 (10/100) and 78Q2121
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* (100Mbps only) MII transceivers. The first PHY available which worked at
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* both 5.0 and 3.3V. Used on the 3Com 3c574 and Ositech products. The OUI
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* is 00:c0:39, models 20 and 21. Warning: The older revision 3 part has
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* several bugs. It always responds to MDIO address 0, and has clear-only
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* semantics for the capability-advertise registers. The current (3/99)
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* revision 11 part, shipping since 8/98, has reportedly fixed these problems.
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*/
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#define MII_TQPHY_VENDOR 0x10 /* Vendor specific register */
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#define VENDOR_RPTR 0x8000 /* Repeater mode */
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#define VENDOR_INTLEVEL 0x4000 /* INTR pin level */
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#define VENDOR_RSVD1 0x2000 /* Reserved */
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#define VENDOR_TXHIM 0x1000 /* Transmit high impedance */
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#define VENDOR_SEQTESTINHIBIT 0x0800 /* Disables 10baseT SQE testing */
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#define VENDOR_10BT_LOOPBACK 0x0400 /* 10baseT natural loopback */
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#define VENDOR_GPIO1_DAT 0x0200 /* General purpose I/O 1 data */
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#define VENDOR_GPIO1_DIR 0x0100 /* General purpose I/O 1 direction */
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#define VENDOR_GPIO0_DAT 0x0080 /* General purpose I/O 0 data */
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#define VENDOR_GPIO0_DIR 0x0040 /* General purpose I/O 0 direction */
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#define VENDOR_APOL 0x0020 /* Auto polarity */
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#define VENDOR_RVSPOL 0x0010 /* Reverse polarity */
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#define VENDOR_RSVD2 0x0008 /* Reserved (must be zero) */
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#define VENDOR_RSVD3 0x0004 /* Reserved (must be zero) */
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#define VENDOR_PCSBP 0x0002 /* PCS bypass */
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#define VENDOR_RXCC 0x0001 /* Receive clock control */
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#define MII_TQPHY_INTR 0x11 /* Interrupt control/status register */
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#define INTR_JABBER_IE 0x8000 /* Jabber interrupt enable */
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#define INTR_RXER_IE 0x4000 /* Receive error enable */
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#define INTR_PRX_IE 0x2000 /* Page received enable */
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#define INTR_PFD_IE 0x1000 /* Parallel detect fault enable */
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#define INTR_LPACK_IE 0x0800 /* Link partner ack. enable */
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#define INTR_LSCHG_IE 0x0400 /* Link status change enable */
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#define INTR_RFAULT_IE 0x0200 /* Remote fault enable */
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#define INTR_ANEGCOMP_IE 0x0100 /* Autonegotiation complete enable */
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#define INTR_JABBER_INT 0x0080 /* Jabber interrupt */
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#define INTR_RXER_INT 0x0040 /* Receive error interrupt */
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#define INTR_PRX_INT 0x0020 /* Page receive interrupt */
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#define INTR_PDF_INT 0x0010 /* Parallel detect fault interrupt */
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#define INTR_LPACK_INT 0x0008 /* Link partner ack. interrupt */
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#define INTR_LSCHG_INT 0x0004 /* Link status change interrupt */
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#define INTR_RFAULT_INT 0x0002 /* Remote fault interrupt */
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#define INTR_ANEGCOMP_INT 0x0001 /* Autonegotiation complete interrupt */
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#define MII_TQPHY_DIAG 0x12 /* Diagnostic register */
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#define DIAG_ANEGF 0x1000 /* Autonegotiation fail */
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#define DIAG_DPLX 0x0800 /* Duplex (half/full) */
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#define DIAG_RATE 0x0400 /* Rate (10/100) */
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#define DIAG_RXPASS 0x0200 /* Receive pass */
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#define DIAG_RXLOCK 0x0100 /* Receive lock */
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#endif /* _DEV_MII_TQPHYREG_H_ */
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