382 lines
14 KiB
C
382 lines
14 KiB
C
/* $NetBSD: sccreg.h,v 1.4 1994/10/26 21:09:17 cgd Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)sccreg.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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/*
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* Definitions for Intel 82530 serial communications chip.
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* Each chip is a dual uart with the A channels used for the keyboard and
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* mouse with the B channel(s) for comm ports with modem control. Since
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* some registers are used for the other channel, the following macros
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* are used to access the register ports.
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*/
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typedef struct {
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/* Channel B is first, then A */
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struct {
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char scc_pad0;
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volatile u_char scc_command; /* reg select */
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char scc_pad1[3];
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volatile u_char scc_data; /* Rx/Tx buffer */
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char scc_pad3[2];
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} scc_channel[2];
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} scc_regmap_t;
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#define SCC_CHANNEL_A 1
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#define SCC_CHANNEL_B 0
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#define SCC_INIT_REG(scc,chan) { \
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char tmp; \
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tmp = (scc)->scc_channel[(chan)].scc_command; \
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tmp = (scc)->scc_channel[(chan)].scc_command; \
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}
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#define SCC_READ_REG(scc,chan,reg,val) { \
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(scc)->scc_channel[(chan)].scc_command = (reg); \
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(val) = (scc)->scc_channel[(chan)].scc_command; \
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}
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#define SCC_READ_REG_ZERO(scc,chan,val) { \
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(val) = (scc)->scc_channel[(chan)].scc_command; \
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}
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#define SCC_WRITE_REG(scc,chan,reg,val) { \
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(scc)->scc_channel[(chan)].scc_command = (reg); \
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(scc)->scc_channel[(chan)].scc_command = (val); \
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}
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#define SCC_WRITE_REG_ZERO(scc,chan,val) { \
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(scc)->scc_channel[(chan)].scc_command = (val); \
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}
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#define SCC_READ_DATA(scc,chan,val) { \
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(val) = (scc)->scc_channel[(chan)].scc_data; \
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}
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#define SCC_WRITE_DATA(scc,chan,val) { \
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(scc)->scc_channel[(chan)].scc_data = (val); \
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}
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#define SCC_RR0 0 /* status register */
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#define SCC_RR1 1 /* special receive conditions */
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#define SCC_RR2 2 /* (modified) interrupt vector */
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#define SCC_RR3 3 /* interrupts pending (cha A only) */
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#define SCC_RR8 8 /* recv buffer (alias for data) */
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#define SCC_RR10 10 /* sdlc status */
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#define SCC_RR12 12 /* BRG constant, low part */
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#define SCC_RR13 13 /* BRG constant, high part */
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#define SCC_RR15 15 /* interrupts currently enabled */
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#define SCC_WR0 0 /* reg select, and commands */
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#define SCC_WR1 1 /* interrupt and DMA enables */
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#define SCC_WR2 2 /* interrupt vector */
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#define SCC_WR3 3 /* receiver params and enables */
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#define SCC_WR4 4 /* clock/char/parity params */
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#define SCC_WR5 5 /* xmit params and enables */
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#define SCC_WR6 6 /* synchr SYNCH/address */
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#define SCC_WR7 7 /* synchr SYNCH/flag */
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#define SCC_WR8 8 /* xmit buffer (alias for data) */
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#define SCC_WR9 9 /* vectoring and resets */
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#define SCC_WR10 10 /* synchr params */
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#define SCC_WR11 11 /* clocking definitions */
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#define SCC_WR12 12 /* BRG constant, low part */
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#define SCC_WR13 13 /* BRG constant, high part */
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#define SCC_WR14 14 /* BRG enables and commands */
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#define SCC_WR15 15 /* interrupt enables */
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/*
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* Read registers defines
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*/
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#define SCC_RR0_BREAK 0x80 /* break detected (rings twice), or */
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#define SCC_RR0_ABORT 0x80 /* abort (synchr) */
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#define SCC_RR0_TX_UNDERRUN 0x40 /* xmit buffer empty/end of message */
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#define SCC_RR0_CTS 0x20 /* clear-to-send pin active (sampled
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only on intr and after RESI cmd */
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#define SCC_RR0_SYNCH 0x10 /* SYNCH found/still hunting */
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#define SCC_RR0_DCD 0x08 /* carrier-detect (same as CTS) */
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#define SCC_RR0_TX_EMPTY 0x04 /* xmit buffer empty */
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#define SCC_RR0_ZERO_COUNT 0x02 /* ? */
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#define SCC_RR0_RX_AVAIL 0x01 /* recv fifo not empty */
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#define SCC_RR1_EOF 0x80 /* end-of-frame, SDLC mode */
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#define SCC_RR1_CRC_ERR 0x40 /* incorrect CRC or.. */
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#define SCC_RR1_FRAME_ERR 0x40 /* ..bad frame */
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#define SCC_RR1_RX_OVERRUN 0x20 /* rcv fifo overflow */
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#define SCC_RR1_PARITY_ERR 0x10 /* incorrect parity in data */
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#define SCC_RR1_RESIDUE0 0x08
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#define SCC_RR1_RESIDUE1 0x04
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#define SCC_RR1_RESIDUE2 0x02
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#define SCC_RR1_ALL_SENT 0x01
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/* RR2 contains the interrupt vector unmodified (channel A) or
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modified as follows (channel B, if vector-include-status) */
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#define SCC_RR2_STATUS(val) ((val)&0xf)
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#define SCC_RR2_B_XMIT_DONE 0x0
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#define SCC_RR2_B_EXT_STATUS 0x2
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#define SCC_RR2_B_RECV_DONE 0x4
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#define SCC_RR2_B_RECV_SPECIAL 0x6
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#define SCC_RR2_A_XMIT_DONE 0x8
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#define SCC_RR2_A_EXT_STATUS 0xa
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#define SCC_RR2_A_RECV_DONE 0xc
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#define SCC_RR2_A_RECV_SPECIAL 0xe
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/* Interrupts pending, to be read from channel A only (B raz) */
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#define SCC_RR3_zero 0xc0
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#define SCC_RR3_RX_IP_A 0x20
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#define SCC_RR3_TX_IP_A 0x10
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#define SCC_RR3_EXT_IP_A 0x08
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#define SCC_RR3_RX_IP_B 0x04
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#define SCC_RR3_TX_IP_B 0x02
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#define SCC_RR3_EXT_IP_B 0x01
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/* RR8 is the receive data buffer, a 3 deep FIFO */
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#define SCC_RECV_BUFFER SCC_RR8
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#define SCC_RECV_FIFO_DEEP 3
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#define SCC_RR10_1CLKS 0x80
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#define SCC_RR10_2CLKS 0x40
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#define SCC_RR10_zero 0x2d
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#define SCC_RR10_LOOP_SND 0x10
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#define SCC_RR10_ON_LOOP 0x02
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/* RR12/RR13 hold the timing base, upper byte in RR13 */
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#define SCC_GET_TIMING_BASE(scc,chan,val) { \
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register char tmp; \
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SCC_READ_REG(scc,chan,SCC_RR12,val);\
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SCC_READ_REG(scc,chan,SCC_RR13,tmp);\
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(val) = ((val)<<8)|(tmp&0xff);\
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}
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#define SCC_RR15_BREAK_IE 0x80
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#define SCC_RR15_TX_UNDERRUN_IE 0x40
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#define SCC_RR15_CTS_IE 0x20
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#define SCC_RR15_SYNCH_IE 0x10
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#define SCC_RR15_DCD_IE 0x08
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#define SCC_RR15_zero 0x05
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#define SCC_RR15_ZERO_COUNT_IE 0x02
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/*
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* Write registers defines
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*/
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/* WR0 is used for commands too */
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#define SCC_RESET_TXURUN_LATCH 0xc0
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#define SCC_RESET_TX_CRC 0x80
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#define SCC_RESET_RX_CRC 0x40
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#define SCC_RESET_HIGHEST_IUS 0x38 /* channel A only */
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#define SCC_RESET_ERROR 0x30
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#define SCC_RESET_TX_IP 0x28
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#define SCC_IE_NEXT_CHAR 0x20
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#define SCC_SEND_SDLC_ABORT 0x18
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#define SCC_RESET_EXT_IP 0x10
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#define SCC_WR1_DMA_ENABLE 0x80 /* dma control */
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#define SCC_WR1_DMA_MODE 0x40 /* drive ~req for DMA controller */
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#define SCC_WR1_DMA_RECV_DATA 0x20 /* from wire to host memory */
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/* interrupt enable/conditions */
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#define SCC_WR1_RXI_SPECIAL_O 0x18 /* on special only */
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#define SCC_WR1_RXI_ALL_CHAR 0x10 /* on each char, or special */
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#define SCC_WR1_RXI_FIRST_CHAR 0x08 /* on first char, or special */
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#define SCC_WR1_RXI_DISABLE 0x00 /* never on recv */
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#define SCC_WR1_PARITY_IE 0x04 /* on parity errors */
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#define SCC_WR1_TX_IE 0x02
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#define SCC_WR1_EXT_IE 0x01
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/* WR2 is common and contains the interrupt vector (high nibble) */
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#define SCC_WR3_RX_8_BITS 0xc0
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#define SCC_WR3_RX_6_BITS 0x80
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#define SCC_WR3_RX_7_BITS 0x40
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#define SCC_WR3_RX_5_BITS 0x00
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#define SCC_WR3_AUTO_ENABLE 0x20
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#define SCC_WR3_HUNT_MODE 0x10
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#define SCC_WR3_RX_CRC_ENABLE 0x08
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#define SCC_WR3_SDLC_SRCH 0x04
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#define SCC_WR3_INHIBIT_SYNCH 0x02
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#define SCC_WR3_RX_ENABLE 0x01
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/* Should be re-written after reset */
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#define SCC_WR4_CLK_x64 0xc0 /* clock divide factor */
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#define SCC_WR4_CLK_x32 0x80
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#define SCC_WR4_CLK_x16 0x40
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#define SCC_WR4_CLK_x1 0x00
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#define SCC_WR4_EXT_SYNCH_MODE 0x30 /* synch modes */
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#define SCC_WR4_SDLC_MODE 0x20
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#define SCC_WR4_16BIT_SYNCH 0x10
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#define SCC_WR4_8BIT_SYNCH 0x00
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#define SCC_WR4_2_STOP 0x0c /* asynch modes */
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#define SCC_WR4_1_5_STOP 0x08
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#define SCC_WR4_1_STOP 0x04
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#define SCC_WR4_SYNCH_MODE 0x00
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#define SCC_WR4_EVEN_PARITY 0x02
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#define SCC_WR4_PARITY_ENABLE 0x01
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#define SCC_WR5_DTR 0x80 /* drive DTR pin */
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#define SCC_WR5_TX_8_BITS 0x60
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#define SCC_WR5_TX_6_BITS 0x40
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#define SCC_WR5_TX_7_BITS 0x20
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#define SCC_WR5_TX_5_BITS 0x00
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#define SCC_WR5_SEND_BREAK 0x10
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#define SCC_WR5_TX_ENABLE 0x08
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#define SCC_WR5_CRC_16 0x04 /* CRC if non zero, .. */
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#define SCC_WR5_SDLC 0x00 /* ..SDLC otherwise */
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#define SCC_WR5_RTS 0x02 /* drive RTS pin */
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#define SCC_WR5_TX_CRC_ENABLE 0x01
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/* Registers WR6 and WR7 are for synch modes data, with among other things: */
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#define SCC_WR6_BISYNCH_12 0x0f
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#define SCC_WR6_SDLC_RANGE_MASK 0x0f
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#define SCC_WR7_SDLC_FLAG 0x7e
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/* WR8 is the transmit data buffer (no FIFO) */
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#define SCC_XMT_BUFFER SCC_WR8
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#define SCC_WR9_HW_RESET 0xc0 /* force hardware reset */
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#define SCC_WR9_RESET_CHA_A 0x80
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#define SCC_WR9_RESET_CHA_B 0x40
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#define SCC_WR9_NON_VECTORED 0x20 /* mbz for Zilog chip */
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#define SCC_WR9_STATUS_HIGH 0x10
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#define SCC_WR9_MASTER_IE 0x08
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#define SCC_WR9_DLC 0x04 /* disable-lower-chain */
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#define SCC_WR9_NV 0x02 /* no vector */
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#define SCC_WR9_VIS 0x01 /* vector-includes-status */
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#define SCC_WR10_CRC_PRESET 0x80
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#define SCC_WR10_FM0 0x60
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#define SCC_WR10_FM1 0x40
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#define SCC_WR10_NRZI 0x20
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#define SCC_WR10_NRZ 0x00
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#define SCC_WR10_ACTIVE_ON_POLL 0x10
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#define SCC_WR10_MARK_IDLE 0x08 /* flag if zero */
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#define SCC_WR10_ABORT_ON_URUN 0x04 /* flag if zero */
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#define SCC_WR10_LOOP_MODE 0x02
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#define SCC_WR10_6BIT_SYNCH 0x01
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#define SCC_WR10_8BIT_SYNCH 0x00
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#define SCC_WR11_RTxC_XTAL 0x80 /* RTxC pin is input (ext oscill) */
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#define SCC_WR11_RCLK_DPLL 0x60 /* clock received data on dpll */
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#define SCC_WR11_RCLK_BAUDR 0x40 /* .. on BRG */
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#define SCC_WR11_RCLK_TRc_PIN 0x20 /* .. on TRxC pin */
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#define SCC_WR11_RCLK_RTc_PIN 0x00 /* .. on RTxC pin */
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#define SCC_WR11_XTLK_DPLL 0x18
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#define SCC_WR11_XTLK_BAUDR 0x10
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#define SCC_WR11_XTLK_TRc_PIN 0x08
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#define SCC_WR11_XTLK_RTc_PIN 0x00
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#define SCC_WR11_TRc_OUT 0x04 /* drive TRxC pin as output from..*/
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#define SCC_WR11_TRcOUT_DPLL 0x03 /* .. the dpll */
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#define SCC_WR11_TRcOUT_BAUDR 0x02 /* .. the BRG */
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#define SCC_WR11_TRcOUT_XMTCLK 0x01 /* .. the xmit clock */
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#define SCC_WR11_TRcOUT_XTAL 0x00 /* .. the external oscillator */
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/* WR12/WR13 are for timing base preset */
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#define SCC_SET_TIMING_BASE(scc,chan,val) { \
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SCC_WRITE_REG(scc,chan,SCC_RR12,val);\
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SCC_WRITE_REG(scc,chan,SCC_RR13,(val)>>8);\
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}
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/* More commands in this register */
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#define SCC_WR14_NRZI_MODE 0xe0 /* synch modulations */
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#define SCC_WR14_FM_MODE 0xc0
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#define SCC_WR14_RTc_SOURCE 0xa0 /* clock is from pin .. */
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#define SCC_WR14_BAUDR_SOURCE 0x80 /* .. or internal BRG */
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#define SCC_WR14_DISABLE_DPLL 0x60
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#define SCC_WR14_RESET_CLKMISS 0x40
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#define SCC_WR14_SEARCH_MODE 0x20
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/* ..and more bitsy */
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#define SCC_WR14_LOCAL_LOOPB 0x10
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#define SCC_WR14_AUTO_ECHO 0x08
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#define SCC_WR14_DTR_REQUEST 0x04
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#define SCC_WR14_BAUDR_SRC 0x02
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#define SCC_WR14_BAUDR_ENABLE 0x01
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#define SCC_WR15_BREAK_IE 0x80
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#define SCC_WR15_TX_UNDERRUN_IE 0x40
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#define SCC_WR15_CTS_IE 0x20
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#define SCC_WR15_SYNCHUNT_IE 0x10
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#define SCC_WR15_DCD_IE 0x08
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#define SCC_WR15_zero 0x05
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#define SCC_WR15_ZERO_COUNT_IE 0x02
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/* bits in dm lsr, copied from dmreg.h */
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#define DML_DSR 0000400 /* data set ready, not a real DM bit */
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#define DML_RNG 0000200 /* ring */
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#define DML_CAR 0000100 /* carrier detect */
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#define DML_CTS 0000040 /* clear to send */
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#define DML_SR 0000020 /* secondary receive */
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#define DML_ST 0000010 /* secondary transmit */
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#define DML_RTS 0000004 /* request to send */
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#define DML_DTR 0000002 /* data terminal ready */
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#define DML_LE 0000001 /* line enable */
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/*
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* Minor device numbers for scc. Weird because B channel comes
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* first and the A channels are wired for keyboard/mouse and the
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* B channels for the comm port(s).
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*/
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#define SCCCOMM2_PORT 0x0
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#define SCCMOUSE_PORT 0x1
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#define SCCCOMM3_PORT 0x2
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#define SCCKBD_PORT 0x3
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