1241 lines
30 KiB
C
1241 lines
30 KiB
C
/* $NetBSD: sdhc.c,v 1.7 2010/03/27 03:04:52 nonaka Exp $ */
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/* $OpenBSD: sdhc.c,v 1.25 2009/01/13 19:44:20 grange Exp $ */
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* SD Host Controller driver based on the SD Host Controller Standard
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* Simplified Specification Version 1.00 (www.sdcard.com).
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: sdhc.c,v 1.7 2010/03/27 03:04:52 nonaka Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <sys/mutex.h>
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#include <sys/condvar.h>
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#include <dev/sdmmc/sdhcreg.h>
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#include <dev/sdmmc/sdhcvar.h>
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#include <dev/sdmmc/sdmmcchip.h>
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#include <dev/sdmmc/sdmmcreg.h>
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#include <dev/sdmmc/sdmmcvar.h>
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#ifdef SDHC_DEBUG
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int sdhcdebug = 1;
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#define DPRINTF(n,s) do { if ((n) <= sdhcdebug) printf s; } while (0)
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void sdhc_dump_regs(struct sdhc_host *);
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#else
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#define DPRINTF(n,s) do {} while (0)
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#endif
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#define SDHC_COMMAND_TIMEOUT hz
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#define SDHC_BUFFER_TIMEOUT hz
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#define SDHC_TRANSFER_TIMEOUT hz
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#define SDHC_DMA_TIMEOUT hz
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struct sdhc_host {
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struct sdhc_softc *sc; /* host controller device */
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bus_space_tag_t iot; /* host register set tag */
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bus_space_handle_t ioh; /* host register set handle */
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bus_dma_tag_t dmat; /* host DMA tag */
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device_t sdmmc; /* generic SD/MMC device */
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struct kmutex host_mtx;
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u_int clkbase; /* base clock frequency in KHz */
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int maxblklen; /* maximum block length */
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uint32_t ocr; /* OCR value from capabilities */
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uint8_t regs[14]; /* host controller state */
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uint16_t intr_status; /* soft interrupt status */
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uint16_t intr_error_status; /* soft error status */
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struct kmutex intr_mtx;
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struct kcondvar intr_cv;
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uint32_t flags; /* flags for this host */
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#define SHF_USE_DMA 0x0001
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#define SHF_USE_4BIT_MODE 0x0002
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};
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#define HDEVNAME(hp) (device_xname((hp)->sc->sc_dev))
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#define HREAD1(hp, reg) \
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(bus_space_read_1((hp)->iot, (hp)->ioh, (reg)))
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#define HREAD2(hp, reg) \
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(bus_space_read_2((hp)->iot, (hp)->ioh, (reg)))
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#define HREAD4(hp, reg) \
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(bus_space_read_4((hp)->iot, (hp)->ioh, (reg)))
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#define HWRITE1(hp, reg, val) \
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bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val))
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#define HWRITE2(hp, reg, val) \
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bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val))
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#define HWRITE4(hp, reg, val) \
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bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))
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#define HCLR1(hp, reg, bits) \
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HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))
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#define HCLR2(hp, reg, bits) \
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HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits))
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#define HSET1(hp, reg, bits) \
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HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))
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#define HSET2(hp, reg, bits) \
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HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits))
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static int sdhc_host_reset(sdmmc_chipset_handle_t);
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static int sdhc_host_reset1(sdmmc_chipset_handle_t);
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static uint32_t sdhc_host_ocr(sdmmc_chipset_handle_t);
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static int sdhc_host_maxblklen(sdmmc_chipset_handle_t);
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static int sdhc_card_detect(sdmmc_chipset_handle_t);
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static int sdhc_write_protect(sdmmc_chipset_handle_t);
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static int sdhc_bus_power(sdmmc_chipset_handle_t, uint32_t);
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static int sdhc_bus_clock(sdmmc_chipset_handle_t, int);
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static int sdhc_bus_width(sdmmc_chipset_handle_t, int);
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static void sdhc_card_enable_intr(sdmmc_chipset_handle_t, int);
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static void sdhc_card_intr_ack(sdmmc_chipset_handle_t);
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static void sdhc_exec_command(sdmmc_chipset_handle_t,
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struct sdmmc_command *);
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static int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *);
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static int sdhc_wait_state(struct sdhc_host *, uint32_t, uint32_t);
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static int sdhc_soft_reset(struct sdhc_host *, int);
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static int sdhc_wait_intr(struct sdhc_host *, int, int);
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static void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *);
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static int sdhc_transfer_data_dma(struct sdhc_host *, struct sdmmc_command *);
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static int sdhc_transfer_data_pio(struct sdhc_host *, struct sdmmc_command *);
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static void sdhc_read_data_pio(struct sdhc_host *, uint8_t *, int);
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static void sdhc_write_data_pio(struct sdhc_host *, uint8_t *, int);
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static struct sdmmc_chip_functions sdhc_functions = {
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/* host controller reset */
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sdhc_host_reset,
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/* host controller capabilities */
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sdhc_host_ocr,
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sdhc_host_maxblklen,
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/* card detection */
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sdhc_card_detect,
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/* write protect */
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sdhc_write_protect,
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/* bus power, clock frequency and width */
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sdhc_bus_power,
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sdhc_bus_clock,
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sdhc_bus_width,
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/* command execution */
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sdhc_exec_command,
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/* card interrupt */
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sdhc_card_enable_intr,
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sdhc_card_intr_ack
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};
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/*
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* Called by attachment driver. For each SD card slot there is one SD
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* host controller standard register set. (1.3)
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*/
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int
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sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
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bus_space_handle_t ioh, bus_size_t iosize)
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{
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struct sdmmcbus_attach_args saa;
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struct sdhc_host *hp;
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uint32_t caps;
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#ifdef SDHC_DEBUG
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uint16_t sdhcver;
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sdhcver = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION);
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aprint_normal_dev(sc->sc_dev, "SD Host Specification/Vendor Version ");
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switch (SDHC_SPEC_VERSION(sdhcver)) {
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case 0x00:
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aprint_normal("1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver));
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break;
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default:
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aprint_normal(">1.0/%u\n", SDHC_VENDOR_VERSION(sdhcver));
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break;
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}
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#endif
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/* Allocate one more host structure. */
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hp = malloc(sizeof(struct sdhc_host), M_DEVBUF, M_WAITOK|M_ZERO);
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if (hp == NULL) {
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aprint_error_dev(sc->sc_dev,
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"couldn't alloc memory (sdhc host)\n");
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goto err1;
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}
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sc->sc_host[sc->sc_nhosts++] = hp;
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/* Fill in the new host structure. */
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hp->sc = sc;
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hp->iot = iot;
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hp->ioh = ioh;
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hp->dmat = sc->sc_dmat;
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mutex_init(&hp->host_mtx, MUTEX_DEFAULT, IPL_SDMMC);
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mutex_init(&hp->intr_mtx, MUTEX_DEFAULT, IPL_SDMMC);
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cv_init(&hp->intr_cv, "sdhcintr");
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/*
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* Reset the host controller and enable interrupts.
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*/
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(void)sdhc_host_reset(hp);
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/* Determine host capabilities. */
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mutex_enter(&hp->host_mtx);
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caps = HREAD4(hp, SDHC_CAPABILITIES);
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mutex_exit(&hp->host_mtx);
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#if notyet
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/* Use DMA if the host system and the controller support it. */
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if (ISSET(sc->sc_flags, SDHC_FLAG_FORCE_DMA)
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|| ((ISSET(sc->sc_flags, SDHC_FLAG_USE_DMA)
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&& ISSET(caps, SDHC_DMA_SUPPORT)))) {
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SET(hp->flags, SHF_USE_DMA);
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aprint_normal_dev(sc->sc_dev, "using DMA transfer\n");
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}
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#endif
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/*
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* Determine the base clock frequency. (2.2.24)
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*/
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if (SDHC_BASE_FREQ_KHZ(caps) != 0)
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hp->clkbase = SDHC_BASE_FREQ_KHZ(caps);
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if (hp->clkbase == 0) {
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/* The attachment driver must tell us. */
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aprint_error_dev(sc->sc_dev, "unknown base clock frequency\n");
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goto err;
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} else if (hp->clkbase < 10000 || hp->clkbase > 63000) {
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/* SDHC 1.0 supports only 10-63 MHz. */
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aprint_error_dev(sc->sc_dev,
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"base clock frequency out of range: %u MHz\n",
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hp->clkbase / 1000);
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goto err;
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}
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DPRINTF(1,("%s: base clock frequency %u MHz\n",
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device_xname(sc->sc_dev), hp->clkbase / 1000));
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/*
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* XXX Set the data timeout counter value according to
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* capabilities. (2.2.15)
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*/
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HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX);
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/*
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* Determine SD bus voltage levels supported by the controller.
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*/
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if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V))
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SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V);
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if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V))
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SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
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if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V))
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SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V);
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/*
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* Determine the maximum block length supported by the host
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* controller. (2.2.24)
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*/
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switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) {
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case SDHC_MAX_BLK_LEN_512:
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hp->maxblklen = 512;
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break;
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case SDHC_MAX_BLK_LEN_1024:
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hp->maxblklen = 1024;
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break;
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case SDHC_MAX_BLK_LEN_2048:
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hp->maxblklen = 2048;
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break;
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default:
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aprint_error_dev(sc->sc_dev, "max block length unknown\n");
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goto err;
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}
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DPRINTF(1, ("%s: max block length %u byte%s\n",
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device_xname(sc->sc_dev), hp->maxblklen,
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hp->maxblklen > 1 ? "s" : ""));
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/*
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* Attach the generic SD/MMC bus driver. (The bus driver must
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* not invoke any chipset functions before it is attached.)
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*/
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memset(&saa, 0, sizeof(saa));
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saa.saa_busname = "sdmmc";
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saa.saa_sct = &sdhc_functions;
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saa.saa_sch = hp;
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saa.saa_dmat = hp->dmat;
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saa.saa_clkmin = hp->clkbase / 256;
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saa.saa_clkmax = hp->clkbase;
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saa.saa_caps = SMC_CAPS_4BIT_MODE|SMC_CAPS_AUTO_STOP;
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#if notyet
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if (ISSET(hp->flags, SHF_USE_DMA))
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saa.saa_caps |= SMC_CAPS_DMA;
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#endif
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hp->sdmmc = config_found(sc->sc_dev, &saa, NULL);
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return 0;
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err:
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cv_destroy(&hp->intr_cv);
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mutex_destroy(&hp->intr_mtx);
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mutex_destroy(&hp->host_mtx);
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free(hp, M_DEVBUF);
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sc->sc_host[--sc->sc_nhosts] = NULL;
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err1:
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return 1;
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}
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int
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sdhc_detach(device_t dev, int flags)
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{
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struct sdhc_host *hp = (struct sdhc_host *)dev;
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struct sdhc_softc *sc = hp->sc;
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int rv = 0;
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if (hp->sdmmc)
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rv = config_detach(hp->sdmmc, flags);
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cv_destroy(&hp->intr_cv);
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mutex_destroy(&hp->intr_mtx);
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mutex_destroy(&hp->host_mtx);
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free(hp, M_DEVBUF);
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sc->sc_host[--sc->sc_nhosts] = NULL;
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return rv;
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}
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bool
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sdhc_suspend(device_t dev, const pmf_qual_t *qual)
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{
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struct sdhc_softc *sc = device_private(dev);
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struct sdhc_host *hp;
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int n, i;
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/* XXX poll for command completion or suspend command
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* in progress */
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/* Save the host controller state. */
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for (n = 0; n < sc->sc_nhosts; n++) {
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hp = sc->sc_host[n];
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for (i = 0; i < sizeof hp->regs; i++)
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hp->regs[i] = HREAD1(hp, i);
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}
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return true;
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}
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bool
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sdhc_resume(device_t dev, const pmf_qual_t *qual)
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{
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struct sdhc_softc *sc = device_private(dev);
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struct sdhc_host *hp;
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int n, i;
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/* Restore the host controller state. */
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for (n = 0; n < sc->sc_nhosts; n++) {
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hp = sc->sc_host[n];
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(void)sdhc_host_reset(hp);
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for (i = 0; i < sizeof hp->regs; i++)
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HWRITE1(hp, i, hp->regs[i]);
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}
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return true;
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}
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bool
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sdhc_shutdown(device_t dev, int flags)
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{
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struct sdhc_softc *sc = device_private(dev);
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struct sdhc_host *hp;
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int i;
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/* XXX chip locks up if we don't disable it before reboot. */
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for (i = 0; i < sc->sc_nhosts; i++) {
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hp = sc->sc_host[i];
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(void)sdhc_host_reset(hp);
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}
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return true;
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}
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/*
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* Reset the host controller. Called during initialization, when
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* cards are removed, upon resume, and during error recovery.
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*/
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static int
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sdhc_host_reset1(sdmmc_chipset_handle_t sch)
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{
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struct sdhc_host *hp = (struct sdhc_host *)sch;
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uint16_t sdhcimask;
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int error;
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/* Don't lock. */
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/* Disable all interrupts. */
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HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0);
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/*
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* Reset the entire host controller and wait up to 100ms for
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* the controller to clear the reset bit.
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*/
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error = sdhc_soft_reset(hp, SDHC_RESET_ALL);
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if (error)
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goto out;
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/* Set data timeout counter value to max for now. */
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HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX);
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/* Enable interrupts. */
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sdhcimask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION |
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SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY |
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SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT |
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SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE;
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HWRITE2(hp, SDHC_NINTR_STATUS_EN, sdhcimask);
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HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK);
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HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, sdhcimask);
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HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK);
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out:
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return error;
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}
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|
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static int
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sdhc_host_reset(sdmmc_chipset_handle_t sch)
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{
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struct sdhc_host *hp = (struct sdhc_host *)sch;
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int error;
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mutex_enter(&hp->host_mtx);
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error = sdhc_host_reset1(sch);
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mutex_exit(&hp->host_mtx);
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return error;
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}
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static uint32_t
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sdhc_host_ocr(sdmmc_chipset_handle_t sch)
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{
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struct sdhc_host *hp = (struct sdhc_host *)sch;
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return hp->ocr;
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}
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static int
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sdhc_host_maxblklen(sdmmc_chipset_handle_t sch)
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{
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struct sdhc_host *hp = (struct sdhc_host *)sch;
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return hp->maxblklen;
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}
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|
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/*
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* Return non-zero if the card is currently inserted.
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*/
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static int
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sdhc_card_detect(sdmmc_chipset_handle_t sch)
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{
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struct sdhc_host *hp = (struct sdhc_host *)sch;
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int r;
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|
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mutex_enter(&hp->host_mtx);
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r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED);
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mutex_exit(&hp->host_mtx);
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if (r)
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return 1;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Return non-zero if the card is currently write-protected.
|
|
*/
|
|
static int
|
|
sdhc_write_protect(sdmmc_chipset_handle_t sch)
|
|
{
|
|
struct sdhc_host *hp = (struct sdhc_host *)sch;
|
|
int r;
|
|
|
|
mutex_enter(&hp->host_mtx);
|
|
r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH);
|
|
mutex_exit(&hp->host_mtx);
|
|
|
|
if (!r)
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set or change SD bus voltage and enable or disable SD bus power.
|
|
* Return zero on success.
|
|
*/
|
|
static int
|
|
sdhc_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr)
|
|
{
|
|
struct sdhc_host *hp = (struct sdhc_host *)sch;
|
|
uint8_t vdd;
|
|
int error = 0;
|
|
|
|
mutex_enter(&hp->host_mtx);
|
|
|
|
/*
|
|
* Disable bus power before voltage change.
|
|
*/
|
|
if (!(hp->sc->sc_flags & SDHC_FLAG_NO_PWR0))
|
|
HWRITE1(hp, SDHC_POWER_CTL, 0);
|
|
|
|
/* If power is disabled, reset the host and return now. */
|
|
if (ocr == 0) {
|
|
(void)sdhc_host_reset1(hp);
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Select the lowest voltage according to capabilities.
|
|
*/
|
|
ocr &= hp->ocr;
|
|
if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V))
|
|
vdd = SDHC_VOLTAGE_1_8V;
|
|
else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V))
|
|
vdd = SDHC_VOLTAGE_3_0V;
|
|
else if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V))
|
|
vdd = SDHC_VOLTAGE_3_3V;
|
|
else {
|
|
/* Unsupported voltage level requested. */
|
|
error = EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Enable bus power. Wait at least 1 ms (or 74 clocks) plus
|
|
* voltage ramp until power rises.
|
|
*/
|
|
HWRITE1(hp, SDHC_POWER_CTL,
|
|
(vdd << SDHC_VOLTAGE_SHIFT) | SDHC_BUS_POWER);
|
|
sdmmc_delay(10000);
|
|
|
|
/*
|
|
* The host system may not power the bus due to battery low,
|
|
* etc. In that case, the host controller should clear the
|
|
* bus power bit.
|
|
*/
|
|
if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) {
|
|
error = ENXIO;
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
mutex_exit(&hp->host_mtx);
|
|
|
|
return error;
|
|
}
|
|
|
|
/*
|
|
* Return the smallest possible base clock frequency divisor value
|
|
* for the CLOCK_CTL register to produce `freq' (KHz).
|
|
*/
|
|
static int
|
|
sdhc_clock_divisor(struct sdhc_host *hp, u_int freq)
|
|
{
|
|
int div;
|
|
|
|
for (div = 1; div <= 256; div *= 2)
|
|
if ((hp->clkbase / div) <= freq)
|
|
return (div / 2);
|
|
/* No divisor found. */
|
|
return -1;
|
|
}
|
|
|
|
/*
|
|
* Set or change SDCLK frequency or disable the SD clock.
|
|
* Return zero on success.
|
|
*/
|
|
static int
|
|
sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
|
|
{
|
|
struct sdhc_host *hp = (struct sdhc_host *)sch;
|
|
int div;
|
|
int timo;
|
|
int error = 0;
|
|
#ifdef DIAGNOSTIC
|
|
int ispresent;
|
|
#endif
|
|
|
|
#ifdef DIAGNOSTIC
|
|
mutex_enter(&hp->host_mtx);
|
|
ispresent = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK);
|
|
mutex_exit(&hp->host_mtx);
|
|
|
|
/* Must not stop the clock if commands are in progress. */
|
|
if (ispresent && sdhc_card_detect(hp))
|
|
printf("%s: sdhc_sdclk_frequency_select: command in progress\n",
|
|
device_xname(hp->sc->sc_dev));
|
|
#endif
|
|
|
|
mutex_enter(&hp->host_mtx);
|
|
|
|
/*
|
|
* Stop SD clock before changing the frequency.
|
|
*/
|
|
HWRITE2(hp, SDHC_CLOCK_CTL, 0);
|
|
if (freq == SDMMC_SDCLK_OFF)
|
|
goto out;
|
|
|
|
/*
|
|
* Set the minimum base clock frequency divisor.
|
|
*/
|
|
if ((div = sdhc_clock_divisor(hp, freq)) < 0) {
|
|
/* Invalid base clock frequency or `freq' value. */
|
|
error = EINVAL;
|
|
goto out;
|
|
}
|
|
HWRITE2(hp, SDHC_CLOCK_CTL, div << SDHC_SDCLK_DIV_SHIFT);
|
|
|
|
/*
|
|
* Start internal clock. Wait 10ms for stabilization.
|
|
*/
|
|
HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE);
|
|
for (timo = 1000; timo > 0; timo--) {
|
|
if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE))
|
|
break;
|
|
sdmmc_delay(10);
|
|
}
|
|
if (timo == 0) {
|
|
error = ETIMEDOUT;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Enable SD clock.
|
|
*/
|
|
HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
|
|
|
|
out:
|
|
mutex_exit(&hp->host_mtx);
|
|
|
|
return error;
|
|
}
|
|
|
|
static int
|
|
sdhc_bus_width(sdmmc_chipset_handle_t sch, int width)
|
|
{
|
|
struct sdhc_host *hp = (struct sdhc_host *)sch;
|
|
int reg;
|
|
|
|
switch (width) {
|
|
case 1:
|
|
case 4:
|
|
break;
|
|
|
|
default:
|
|
DPRINTF(0,("%s: unsupported bus width (%d)\n",
|
|
HDEVNAME(hp), width));
|
|
return 1;
|
|
}
|
|
|
|
mutex_enter(&hp->host_mtx);
|
|
reg = HREAD1(hp, SDHC_HOST_CTL);
|
|
reg &= ~SDHC_4BIT_MODE;
|
|
if (width == 4)
|
|
reg |= SDHC_4BIT_MODE;
|
|
HWRITE1(hp, SDHC_HOST_CTL, reg);
|
|
mutex_exit(&hp->host_mtx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
sdhc_card_enable_intr(sdmmc_chipset_handle_t sch, int enable)
|
|
{
|
|
struct sdhc_host *hp = (struct sdhc_host *)sch;
|
|
|
|
mutex_enter(&hp->host_mtx);
|
|
if (enable) {
|
|
HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
|
|
HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
|
|
} else {
|
|
HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
|
|
HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
|
|
}
|
|
mutex_exit(&hp->host_mtx);
|
|
}
|
|
|
|
static void
|
|
sdhc_card_intr_ack(sdmmc_chipset_handle_t sch)
|
|
{
|
|
struct sdhc_host *hp = (struct sdhc_host *)sch;
|
|
|
|
mutex_enter(&hp->host_mtx);
|
|
HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
|
|
mutex_exit(&hp->host_mtx);
|
|
}
|
|
|
|
static int
|
|
sdhc_wait_state(struct sdhc_host *hp, uint32_t mask, uint32_t value)
|
|
{
|
|
uint32_t state;
|
|
int timeout;
|
|
|
|
for (timeout = 10; timeout > 0; timeout--) {
|
|
if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask) == value)
|
|
return 0;
|
|
sdmmc_delay(10000);
|
|
}
|
|
DPRINTF(0,("%s: timeout waiting for %x (state=%x)\n", HDEVNAME(hp),
|
|
value, state));
|
|
return ETIMEDOUT;
|
|
}
|
|
|
|
static void
|
|
sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
|
|
{
|
|
struct sdhc_host *hp = (struct sdhc_host *)sch;
|
|
int error;
|
|
|
|
/*
|
|
* Start the MMC command, or mark `cmd' as failed and return.
|
|
*/
|
|
error = sdhc_start_command(hp, cmd);
|
|
if (error) {
|
|
cmd->c_error = error;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* Wait until the command phase is done, or until the command
|
|
* is marked done for any other reason.
|
|
*/
|
|
if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE, SDHC_COMMAND_TIMEOUT)) {
|
|
cmd->c_error = ETIMEDOUT;
|
|
goto out;
|
|
}
|
|
|
|
/*
|
|
* The host controller removes bits [0:7] from the response
|
|
* data (CRC) and we pass the data up unchanged to the bus
|
|
* driver (without padding).
|
|
*/
|
|
mutex_enter(&hp->host_mtx);
|
|
if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) {
|
|
if (ISSET(cmd->c_flags, SCF_RSP_136)) {
|
|
uint8_t *p = (uint8_t *)cmd->c_resp;
|
|
int i;
|
|
|
|
for (i = 0; i < 15; i++)
|
|
*p++ = HREAD1(hp, SDHC_RESPONSE + i);
|
|
} else {
|
|
cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE);
|
|
}
|
|
}
|
|
mutex_exit(&hp->host_mtx);
|
|
DPRINTF(1,("%s: resp = %08x\n", HDEVNAME(hp), cmd->c_resp[0]));
|
|
|
|
/*
|
|
* If the command has data to transfer in any direction,
|
|
* execute the transfer now.
|
|
*/
|
|
if (cmd->c_error == 0 && cmd->c_data != NULL)
|
|
sdhc_transfer_data(hp, cmd);
|
|
|
|
out:
|
|
mutex_enter(&hp->host_mtx);
|
|
/* Turn off the LED. */
|
|
HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
|
|
mutex_exit(&hp->host_mtx);
|
|
SET(cmd->c_flags, SCF_ITSDONE);
|
|
|
|
DPRINTF(1,("%s: cmd %d %s (flags=%08x error=%d)\n", HDEVNAME(hp),
|
|
cmd->c_opcode, (cmd->c_error == 0) ? "done" : "abort",
|
|
cmd->c_flags, cmd->c_error));
|
|
}
|
|
|
|
static int
|
|
sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
|
|
{
|
|
uint16_t blksize = 0;
|
|
uint16_t blkcount = 0;
|
|
uint16_t mode;
|
|
uint16_t command;
|
|
int error;
|
|
|
|
DPRINTF(1,("%s: start cmd %d arg=%08x data=%p dlen=%d flags=%08x\n",
|
|
HDEVNAME(hp), cmd->c_opcode, cmd->c_arg, cmd->c_data,
|
|
cmd->c_datalen, cmd->c_flags));
|
|
|
|
/*
|
|
* The maximum block length for commands should be the minimum
|
|
* of the host buffer size and the card buffer size. (1.7.2)
|
|
*/
|
|
|
|
/* Fragment the data into proper blocks. */
|
|
if (cmd->c_datalen > 0) {
|
|
blksize = MIN(cmd->c_datalen, cmd->c_blklen);
|
|
blkcount = cmd->c_datalen / blksize;
|
|
if (cmd->c_datalen % blksize > 0) {
|
|
/* XXX: Split this command. (1.7.4) */
|
|
aprint_error_dev(hp->sc->sc_dev,
|
|
"data not a multiple of %u bytes\n", blksize);
|
|
return EINVAL;
|
|
}
|
|
}
|
|
|
|
/* Check limit imposed by 9-bit block count. (1.7.2) */
|
|
if (blkcount > SDHC_BLOCK_COUNT_MAX) {
|
|
aprint_error_dev(hp->sc->sc_dev, "too much data\n");
|
|
return EINVAL;
|
|
}
|
|
|
|
/* Prepare transfer mode register value. (2.2.5) */
|
|
mode = 0;
|
|
if (ISSET(cmd->c_flags, SCF_CMD_READ))
|
|
mode |= SDHC_READ_MODE;
|
|
if (blkcount > 0) {
|
|
mode |= SDHC_BLOCK_COUNT_ENABLE;
|
|
if (blkcount > 1) {
|
|
mode |= SDHC_MULTI_BLOCK_MODE;
|
|
/* XXX only for memory commands? */
|
|
mode |= SDHC_AUTO_CMD12_ENABLE;
|
|
}
|
|
}
|
|
if (cmd->c_dmamap != NULL && cmd->c_datalen > 0) {
|
|
if (cmd->c_dmamap->dm_nsegs == 1) {
|
|
mode |= SDHC_DMA_ENABLE;
|
|
} else {
|
|
cmd->c_dmamap = NULL;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Prepare command register value. (2.2.6)
|
|
*/
|
|
command =
|
|
(cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) << SDHC_COMMAND_INDEX_SHIFT;
|
|
|
|
if (ISSET(cmd->c_flags, SCF_RSP_CRC))
|
|
command |= SDHC_CRC_CHECK_ENABLE;
|
|
if (ISSET(cmd->c_flags, SCF_RSP_IDX))
|
|
command |= SDHC_INDEX_CHECK_ENABLE;
|
|
if (cmd->c_data != NULL)
|
|
command |= SDHC_DATA_PRESENT_SELECT;
|
|
|
|
if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT))
|
|
command |= SDHC_NO_RESPONSE;
|
|
else if (ISSET(cmd->c_flags, SCF_RSP_136))
|
|
command |= SDHC_RESP_LEN_136;
|
|
else if (ISSET(cmd->c_flags, SCF_RSP_BSY))
|
|
command |= SDHC_RESP_LEN_48_CHK_BUSY;
|
|
else
|
|
command |= SDHC_RESP_LEN_48;
|
|
|
|
/* Wait until command and data inhibit bits are clear. (1.5) */
|
|
error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0);
|
|
if (error)
|
|
return error;
|
|
|
|
DPRINTF(1,("%s: writing cmd: blksize=%d blkcnt=%d mode=%04x cmd=%04x\n",
|
|
HDEVNAME(hp), blksize, blkcount, mode, command));
|
|
|
|
mutex_enter(&hp->host_mtx);
|
|
|
|
/* Alert the user not to remove the card. */
|
|
HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
|
|
|
|
/* Set DMA start address. */
|
|
if (ISSET(mode, SDHC_DMA_ENABLE))
|
|
HWRITE4(hp, SDHC_DMA_ADDR, cmd->c_dmamap->dm_segs[0].ds_addr);
|
|
|
|
/*
|
|
* Start a CPU data transfer. Writing to the high order byte
|
|
* of the SDHC_COMMAND register triggers the SD command. (1.5)
|
|
*/
|
|
HWRITE2(hp, SDHC_TRANSFER_MODE, mode);
|
|
HWRITE2(hp, SDHC_BLOCK_SIZE, blksize);
|
|
if (blkcount > 1)
|
|
HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount);
|
|
HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
|
|
HWRITE2(hp, SDHC_COMMAND, command);
|
|
|
|
mutex_exit(&hp->host_mtx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
|
|
{
|
|
int error;
|
|
|
|
DPRINTF(1,("%s: data transfer: resp=%08x datalen=%u\n", HDEVNAME(hp),
|
|
MMC_R1(cmd->c_resp), cmd->c_datalen));
|
|
|
|
#ifdef SDHC_DEBUG
|
|
/* XXX I forgot why I wanted to know when this happens :-( */
|
|
if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) &&
|
|
ISSET(MMC_R1(cmd->c_resp), 0xcb00)) {
|
|
aprint_error_dev(hp->sc->sc_dev,
|
|
"CMD52/53 error response flags %#x\n",
|
|
MMC_R1(cmd->c_resp) & 0xff00);
|
|
}
|
|
#endif
|
|
|
|
if (cmd->c_dmamap != NULL)
|
|
error = sdhc_transfer_data_dma(hp, cmd);
|
|
else
|
|
error = sdhc_transfer_data_pio(hp, cmd);
|
|
if (error)
|
|
cmd->c_error = error;
|
|
SET(cmd->c_flags, SCF_ITSDONE);
|
|
|
|
DPRINTF(1,("%s: data transfer done (error=%d)\n",
|
|
HDEVNAME(hp), cmd->c_error));
|
|
}
|
|
|
|
static int
|
|
sdhc_transfer_data_dma(struct sdhc_host *hp, struct sdmmc_command *cmd)
|
|
{
|
|
bus_dmamap_t dmap = cmd->c_dmamap;
|
|
uint16_t blklen = cmd->c_blklen;
|
|
uint16_t blkcnt = cmd->c_datalen / blklen;
|
|
uint16_t remain;
|
|
int error = 0;
|
|
|
|
for (;;) {
|
|
if (!sdhc_wait_intr(hp,
|
|
SDHC_DMA_INTERRUPT|SDHC_TRANSFER_COMPLETE,
|
|
SDHC_DMA_TIMEOUT)) {
|
|
error = ETIMEDOUT;
|
|
break;
|
|
}
|
|
|
|
/* single block mode */
|
|
if (blkcnt == 1)
|
|
break;
|
|
|
|
/* multi block mode */
|
|
remain = HREAD2(hp, SDHC_BLOCK_COUNT);
|
|
if (remain == 0)
|
|
break;
|
|
|
|
HWRITE4(hp, SDHC_DMA_ADDR,
|
|
dmap->dm_segs[0].ds_addr + (blkcnt - remain) * blklen);
|
|
}
|
|
|
|
#if 0
|
|
if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE,
|
|
SDHC_TRANSFER_TIMEOUT))
|
|
error = ETIMEDOUT;
|
|
#endif
|
|
|
|
return error;
|
|
}
|
|
|
|
static int
|
|
sdhc_transfer_data_pio(struct sdhc_host *hp, struct sdmmc_command *cmd)
|
|
{
|
|
uint8_t *data = cmd->c_data;
|
|
int len, datalen;
|
|
int mask;
|
|
int error = 0;
|
|
|
|
mask = ISSET(cmd->c_flags, SCF_CMD_READ) ?
|
|
SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE;
|
|
datalen = cmd->c_datalen;
|
|
|
|
while (datalen > 0) {
|
|
if (!sdhc_wait_intr(hp,
|
|
SDHC_BUFFER_READ_READY|SDHC_BUFFER_WRITE_READY,
|
|
SDHC_BUFFER_TIMEOUT)) {
|
|
error = ETIMEDOUT;
|
|
break;
|
|
}
|
|
|
|
error = sdhc_wait_state(hp, mask, mask);
|
|
if (error)
|
|
break;
|
|
|
|
len = MIN(datalen, cmd->c_blklen);
|
|
if (ISSET(cmd->c_flags, SCF_CMD_READ))
|
|
sdhc_read_data_pio(hp, data, len);
|
|
else
|
|
sdhc_write_data_pio(hp, data, len);
|
|
|
|
data += len;
|
|
datalen -= len;
|
|
}
|
|
|
|
if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE,
|
|
SDHC_TRANSFER_TIMEOUT))
|
|
error = ETIMEDOUT;
|
|
|
|
return error;
|
|
}
|
|
|
|
static void
|
|
sdhc_read_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen)
|
|
{
|
|
|
|
if (((__uintptr_t)data & 3) == 0) {
|
|
while (datalen > 3) {
|
|
*(uint32_t *)data = HREAD4(hp, SDHC_DATA);
|
|
data += 4;
|
|
datalen -= 4;
|
|
}
|
|
if (datalen > 1) {
|
|
*(uint16_t *)data = HREAD2(hp, SDHC_DATA);
|
|
data += 2;
|
|
datalen -= 2;
|
|
}
|
|
if (datalen > 0) {
|
|
*data = HREAD1(hp, SDHC_DATA);
|
|
data += 1;
|
|
datalen -= 1;
|
|
}
|
|
} else if (((__uintptr_t)data & 1) == 0) {
|
|
while (datalen > 1) {
|
|
*(uint16_t *)data = HREAD2(hp, SDHC_DATA);
|
|
data += 2;
|
|
datalen -= 2;
|
|
}
|
|
if (datalen > 0) {
|
|
*data = HREAD1(hp, SDHC_DATA);
|
|
data += 1;
|
|
datalen -= 1;
|
|
}
|
|
} else {
|
|
while (datalen > 0) {
|
|
*data = HREAD1(hp, SDHC_DATA);
|
|
data += 1;
|
|
datalen -= 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
sdhc_write_data_pio(struct sdhc_host *hp, uint8_t *data, int datalen)
|
|
{
|
|
|
|
if (((__uintptr_t)data & 3) == 0) {
|
|
while (datalen > 3) {
|
|
HWRITE4(hp, SDHC_DATA, *(uint32_t *)data);
|
|
data += 4;
|
|
datalen -= 4;
|
|
}
|
|
if (datalen > 1) {
|
|
HWRITE2(hp, SDHC_DATA, *(uint16_t *)data);
|
|
data += 2;
|
|
datalen -= 2;
|
|
}
|
|
if (datalen > 0) {
|
|
HWRITE1(hp, SDHC_DATA, *data);
|
|
data += 1;
|
|
datalen -= 1;
|
|
}
|
|
} else if (((__uintptr_t)data & 1) == 0) {
|
|
while (datalen > 1) {
|
|
HWRITE2(hp, SDHC_DATA, *(uint16_t *)data);
|
|
data += 2;
|
|
datalen -= 2;
|
|
}
|
|
if (datalen > 0) {
|
|
HWRITE1(hp, SDHC_DATA, *data);
|
|
data += 1;
|
|
datalen -= 1;
|
|
}
|
|
} else {
|
|
while (datalen > 0) {
|
|
HWRITE1(hp, SDHC_DATA, *data);
|
|
data += 1;
|
|
datalen -= 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Prepare for another command. */
|
|
static int
|
|
sdhc_soft_reset(struct sdhc_host *hp, int mask)
|
|
{
|
|
int timo;
|
|
|
|
DPRINTF(1,("%s: software reset reg=%08x\n", HDEVNAME(hp), mask));
|
|
|
|
HWRITE1(hp, SDHC_SOFTWARE_RESET, mask);
|
|
for (timo = 10; timo > 0; timo--) {
|
|
if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask))
|
|
break;
|
|
sdmmc_delay(10000);
|
|
HWRITE1(hp, SDHC_SOFTWARE_RESET, 0);
|
|
}
|
|
if (timo == 0) {
|
|
DPRINTF(1,("%s: timeout reg=%08x\n", HDEVNAME(hp),
|
|
HREAD1(hp, SDHC_SOFTWARE_RESET)));
|
|
HWRITE1(hp, SDHC_SOFTWARE_RESET, 0);
|
|
return ETIMEDOUT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo)
|
|
{
|
|
int status;
|
|
|
|
mask |= SDHC_ERROR_INTERRUPT;
|
|
|
|
mutex_enter(&hp->intr_mtx);
|
|
status = hp->intr_status & mask;
|
|
while (status == 0) {
|
|
if (cv_timedwait(&hp->intr_cv, &hp->intr_mtx, timo)
|
|
== EWOULDBLOCK) {
|
|
status |= SDHC_ERROR_INTERRUPT;
|
|
break;
|
|
}
|
|
status = hp->intr_status & mask;
|
|
}
|
|
hp->intr_status &= ~status;
|
|
|
|
DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status,
|
|
hp->intr_error_status));
|
|
|
|
/* Command timeout has higher priority than command complete. */
|
|
if (ISSET(status, SDHC_ERROR_INTERRUPT)) {
|
|
hp->intr_error_status = 0;
|
|
(void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD);
|
|
status = 0;
|
|
}
|
|
mutex_exit(&hp->intr_mtx);
|
|
|
|
return status;
|
|
}
|
|
|
|
/*
|
|
* Established by attachment driver at interrupt priority IPL_SDMMC.
|
|
*/
|
|
int
|
|
sdhc_intr(void *arg)
|
|
{
|
|
struct sdhc_softc *sc = (struct sdhc_softc *)arg;
|
|
struct sdhc_host *hp;
|
|
int host;
|
|
int done = 0;
|
|
uint16_t status;
|
|
uint16_t error;
|
|
|
|
/* We got an interrupt, but we don't know from which slot. */
|
|
for (host = 0; host < sc->sc_nhosts; host++) {
|
|
hp = sc->sc_host[host];
|
|
if (hp == NULL)
|
|
continue;
|
|
|
|
/* Find out which interrupts are pending. */
|
|
status = HREAD2(hp, SDHC_NINTR_STATUS);
|
|
if (!ISSET(status, SDHC_NINTR_STATUS_MASK))
|
|
continue; /* no interrupt for us */
|
|
|
|
/* Acknowledge the interrupts we are about to handle. */
|
|
HWRITE2(hp, SDHC_NINTR_STATUS, status);
|
|
DPRINTF(2,("%s: interrupt status=%x\n", HDEVNAME(hp),
|
|
status));
|
|
|
|
if (!ISSET(status, SDHC_NINTR_STATUS_MASK))
|
|
continue;
|
|
|
|
/* Claim this interrupt. */
|
|
done = 1;
|
|
|
|
/*
|
|
* Service error interrupts.
|
|
*/
|
|
if (ISSET(status, SDHC_ERROR_INTERRUPT)) {
|
|
/* Acknowledge error interrupts. */
|
|
error = HREAD2(hp, SDHC_EINTR_STATUS);
|
|
HWRITE2(hp, SDHC_EINTR_STATUS, error);
|
|
DPRINTF(2,("%s: error interrupt, status=%x\n",
|
|
HDEVNAME(hp), error));
|
|
|
|
if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR|
|
|
SDHC_DATA_TIMEOUT_ERROR)) {
|
|
hp->intr_error_status |= error;
|
|
hp->intr_status |= status;
|
|
cv_broadcast(&hp->intr_cv);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Wake up the sdmmc event thread to scan for cards.
|
|
*/
|
|
if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION))
|
|
sdmmc_needs_discover(hp->sdmmc);
|
|
|
|
/*
|
|
* Wake up the blocking process to service command
|
|
* related interrupt(s).
|
|
*/
|
|
if (ISSET(status, SDHC_BUFFER_READ_READY|
|
|
SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE|
|
|
SDHC_TRANSFER_COMPLETE|SDHC_DMA_INTERRUPT)) {
|
|
hp->intr_status |= status;
|
|
cv_broadcast(&hp->intr_cv);
|
|
}
|
|
|
|
/*
|
|
* Service SD card interrupts.
|
|
*/
|
|
if (ISSET(status, SDHC_CARD_INTERRUPT)) {
|
|
DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp)));
|
|
HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
|
|
sdmmc_card_intr(hp->sdmmc);
|
|
}
|
|
}
|
|
|
|
return done;
|
|
}
|
|
|
|
#ifdef SDHC_DEBUG
|
|
void
|
|
sdhc_dump_regs(struct sdhc_host *hp)
|
|
{
|
|
|
|
printf("0x%02x PRESENT_STATE: %x\n", SDHC_PRESENT_STATE,
|
|
HREAD4(hp, SDHC_PRESENT_STATE));
|
|
printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL,
|
|
HREAD1(hp, SDHC_POWER_CTL));
|
|
printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS,
|
|
HREAD2(hp, SDHC_NINTR_STATUS));
|
|
printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS,
|
|
HREAD2(hp, SDHC_EINTR_STATUS));
|
|
printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN,
|
|
HREAD2(hp, SDHC_NINTR_STATUS_EN));
|
|
printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN,
|
|
HREAD2(hp, SDHC_EINTR_STATUS_EN));
|
|
printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN,
|
|
HREAD2(hp, SDHC_NINTR_SIGNAL_EN));
|
|
printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN,
|
|
HREAD2(hp, SDHC_EINTR_SIGNAL_EN));
|
|
printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES,
|
|
HREAD4(hp, SDHC_CAPABILITIES));
|
|
printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES,
|
|
HREAD4(hp, SDHC_MAX_CAPABILITIES));
|
|
}
|
|
#endif
|