277 lines
12 KiB
C
277 lines
12 KiB
C
/* $NetBSD: ohcireg.h,v 1.28 2020/06/03 15:38:02 skrll Exp $ */
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/* $FreeBSD: src/sys/dev/usb/ohcireg.h,v 1.8 1999/11/17 22:33:40 n_hibma Exp $ */
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/*
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson (lennart@augustsson.net) at
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* Carlstedt Research & Technology.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_USB_OHCIREG_H_
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#define _DEV_USB_OHCIREG_H_
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/*** PCI config registers ***/
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#define PCI_CBMEM 0x10 /* configuration base memory */
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#define PCI_INTERFACE_OHCI 0x10
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/*** OHCI registers */
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#define OHCI_REVISION 0x00 /* OHCI revision # */
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#define OHCI_REV_LO_MASK __BITS(3,0)
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#define OHCI_REV_HI_MASK __BITS(7,4)
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#define OHCI_REV_LO(rev) __SHIFTOUT((rev), OHCI_REV_LO_MASK)
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#define OHCI_REV_HI(rev) __SHIFTOUT((rev), OHCI_REV_HI_MASK)
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#define OHCI_REV_LEGACY_MASK __BIT(8)
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#define OHCI_REV_LEGACY(rev) __SHIFTOUT((rev), OHCI_REV_LEGACY_MASK)
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#define OHCI_CONTROL 0x04
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#define OHCI_CBSR_MASK __BITS(1,0) /* Control/Bulk Service Ratio */
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#define OHCI_CBSR_SET(x) __SHIFTIN((x), OHCI_CBSR_MASK)
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#define OHCI_RATIO_1_1 0
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#define OHCI_RATIO_1_2 1
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#define OHCI_RATIO_1_3 2
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#define OHCI_RATIO_1_4 3
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#define OHCI_PLE __BIT(2) /* Periodic List Enable */
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#define OHCI_IE __BIT(3) /* Isochronous Enable */
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#define OHCI_CLE __BIT(4) /* Control List Enable */
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#define OHCI_BLE __BIT(5) /* Bulk List Enable */
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#define OHCI_HCFS_MASK __BITS(7,6) /* HostControllerFunctionalState */
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#define OHCI_SET_HCFS(x) __SHIFTIN((x), OHCI_HCFS_MASK)
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#define OHCI_GET_HCFS(x) __SHIFTOUT((x), OHCI_HCFS_MASK)
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#define OHCI_HCFS_RESET 0
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#define OHCI_HCFS_RESUME 1
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#define OHCI_HCFS_OPERATIONAL 2
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#define OHCI_HCFS_SUSPEND 3
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#define OHCI_IR __BIT(8) /* Interrupt Routing */
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#define OHCI_RWC __BIT(9) /* Remote Wakeup Connected */
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#define OHCI_RWE __BIT(10) /* Remote Wakeup Enabled */
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#define OHCI_COMMAND_STATUS 0x08
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#define OHCI_HCR __BIT(0) /* Host Controller Reset */
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#define OHCI_CLF __BIT(1) /* Control List Filled */
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#define OHCI_BLF __BIT(2) /* Bulk List Filled */
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#define OHCI_OCR __BIT(3) /* Ownership Change Request */
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#define OHCI_SOC_MASK __BITS(17,16) /* Scheduling Overrun Count */
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#define OHCI_INTERRUPT_STATUS 0x0c
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#define OHCI_SO __BIT(0) /* Scheduling Overrun */
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#define OHCI_WDH __BIT(1) /* Writeback Done Head */
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#define OHCI_SF __BIT(2) /* Start of Frame */
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#define OHCI_RD __BIT(3) /* Resume Detected */
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#define OHCI_UE __BIT(4) /* Unrecoverable Error */
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#define OHCI_FNO __BIT(5) /* Frame Number Overflow */
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#define OHCI_RHSC __BIT(6) /* Root Hub Status Change */
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#define OHCI_OC __BIT(30) /* Ownership Change */
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#define OHCI_MIE __BIT(31) /* Master Interrupt Enable */
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#define OHCI_INTERRUPT_ENABLE 0x10
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#define OHCI_INTERRUPT_DISABLE 0x14
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#define OHCI_HCCA 0x18
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#define OHCI_PERIOD_CURRENT_ED 0x1c
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#define OHCI_PERIOD_CURRENT_ED 0x1c
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#define OHCI_CONTROL_HEAD_ED 0x20
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#define OHCI_CONTROL_CURRENT_ED 0x24
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#define OHCI_BULK_HEAD_ED 0x28
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#define OHCI_BULK_CURRENT_ED 0x2c
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#define OHCI_DONE_HEAD 0x30
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#define OHCI_FM_INTERVAL 0x34
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#define OHCI_FM_IVAL_MASK __BITS(13,0)
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#define OHCI_FM_GET_IVAL(x) __SHIFTOUT((x), OHCI_FM_IVAL_MASK)
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#define OHCI_FM_FSMPS_MASK __BITS(30,16)
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#define OHCI_FM_GET_FSMPS(x) __SHIFTOUT((x), OHCI_FM_FSMPS_MASK)
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#define OHCI_FM_SET_FSMPS(x) __SHIFTIN((x), OHCI_FM_FSMPS_MASK)
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#define OHCI_FM_FIT __BIT(31)
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#define OHCI_FM_REMAINING 0x38
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#define OHCI_FM_NUMBER 0x3c
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#define OHCI_PERIODIC_START 0x40
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#define OHCI_LS_THRESHOLD 0x44
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#define OHCI_RH_DESCRIPTOR_A 0x48
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#define OHCI_RHD_NDP_MASK __BITS(7,0)
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#define OHCI_RHD_GET_NDP(x) __SHIFTOUT((x), OHCI_RHD_NDP_MASK)
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#define OHCI_RHD_PSM __BIT(8) /* Power Switching Mode */
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#define OHCI_RHD_NPS __BIT(9) /* No Power Switching */
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#define OHCI_RHD_DT __BIT(10) /* Device Type */
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#define OHCI_RHD_OCPM __BIT(11) /* Overcurrent Protection Mode */
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#define OHCI_RHD_NOCP __BIT(12) /* No Overcurrent Protection */
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#define OHCI_RHD_POTPGT_MASK __BITS(31,24)
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#define OHCI_RHD_GET_POTPGT(x) __SHIFTOUT((x), OHCI_RHD_POTPGT_MASK)
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#define OHCI_RHD_SET_POTPGT(x) __SHIFTIN((x), OHCI_RHD_POTPGT_MASK)
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#define OHCI_RH_DESCRIPTOR_B 0x4c
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#define OHCI_RH_STATUS 0x50
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#define OHCI_RHS_LPS __BIT(0) /* Local Power Status */
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#define OHCI_RHS_OCI __BIT(1) /* OverCurrent Indicator */
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#define OHCI_RHS_DRWE __BIT(15) /* Device Remote Wakeup Enable */
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#define OHCI_RHS_LPSC __BIT(16) /* Local Power Status Change */
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#define OHCI_RHS_CCIC __BIT(17) /* OverCurrent Indicator Change */
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#define OHCI_RHS_CRWE __BIT(31) /* Clear Remote Wakeup Enable */
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#define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) /* 1 based indexing */
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#define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE)
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#define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | \
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OHCI_FNO | OHCI_RHSC | OHCI_OC)
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#define OHCI_NORMAL_INTRS (OHCI_SO | OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC)
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#define OHCI_FSMPS(i) (((i-210)*6/7) << 16)
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#define OHCI_PERIODIC(i) ((i)*9/10)
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typedef uint32_t ohci_physaddr_t;
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#define OHCI_NO_INTRS 32
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struct ohci_hcca {
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volatile ohci_physaddr_t hcca_interrupt_table[OHCI_NO_INTRS];
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volatile uint32_t hcca_frame_number;
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volatile ohci_physaddr_t hcca_done_head;
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#define OHCI_DONE_INTRS 1
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};
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#define OHCI_HCCA_SIZE 256
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#define OHCI_HCCA_ALIGN 256
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#define OHCI_PAGE_SIZE 0x1000
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#define OHCI_PAGE(x) ((x) &~ 0xfff)
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#define OHCI_PAGE_OFFSET(x) ((x) & 0xfff)
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typedef struct {
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volatile uint32_t ed_flags;
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#define OHCI_ED_ADDR_MASK __BITS(6,0)
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#define OHCI_ED_GET_FA(x) __SHIFTOUT((x), OHCI_ED_ADDR_MASK)
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#define OHCI_ED_SET_FA(x) __SHIFTIN((x), OHCI_ED_ADDR_MASK)
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#define OHCI_ED_EN_MASK __BITS(10,7)
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#define OHCI_ED_GET_EN(x) __SHIFTOUT((x), OHCI_ED_EN_MASK)
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#define OHCI_ED_SET_EN(x) __SHIFTIN((x), OHCI_ED_EN_MASK)
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#define OHCI_ED_DIR_MASK __BITS(12,11)
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#define OHCI_ED_GET_DIR(x) __SHIFTOUT((x), OHCI_ED_DIR_MASK)
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#define OHCI_ED_SET_DIR(x) __SHIFTIN((x), OHCI_ED_DIR_MASK)
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#define OHCI_ED_DIR_TD 0
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#define OHCI_ED_DIR_OUT 1
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#define OHCI_ED_DIR_IN 2
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#define OHCI_ED_SPEED __BIT(13)
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#define OHCI_ED_SKIP __BIT(14)
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#define OHCI_ED_FORMAT_MASK __BIT(15)
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#define OHCI_ED_GET_FORMAT(x) __SHIFTOUT((x), OHCI_ED_FORMAT_MASK)
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#define OHCI_ED_SET_FORMAT(x) __SHIFTIN((x), OHCI_ED_FORMAT_MASK)
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#define OHCI_ED_FORMAT_GEN 0
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#define OHCI_ED_FORMAT_ISO 1
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#define OHCI_ED_MAXP_MASK __BITS(26,16)
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#define OHCI_ED_GET_MAXP(x) __SHIFTOUT((x), OHCI_ED_MAXP_MASK)
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#define OHCI_ED_SET_MAXP(x) __SHIFTIN((x), OHCI_ED_MAXP_MASK)
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volatile ohci_physaddr_t ed_tailp;
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volatile ohci_physaddr_t ed_headp;
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#define OHCI_HALTED __BIT(0)
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#define OHCI_TOGGLECARRY __BIT(1)
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#define OHCI_HEADMASK __BITS(31,2)
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volatile ohci_physaddr_t ed_nexted;
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} ohci_ed_t;
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/* #define OHCI_ED_SIZE 16 */
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#define OHCI_ED_ALIGN 16
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typedef struct {
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volatile uint32_t td_flags;
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#define OHCI_TD_R __BIT(18) /* Buffer Rounding */
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#define OHCI_TD_DP_MASK __BITS(20,19) /* Direction / PID */
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#define OHCI_TD_GET_DP(x) __SHIFTOUT((x), OHCI_TD_DP_MASK)
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#define OHCI_TD_SET_DP(x) __SHIFTIN((x), OHCI_TD_DP_MASK)
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#define OHCI_TD_DP_SETUP 0
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#define OHCI_TD_DP_OUT 1
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#define OHCI_TD_DP_IN 2
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#define OHCI_TD_DI_MASK __BITS(23,21) /* Delay Interrupt */
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#define OHCI_TD_GET_DI(x) __SHIFTOUT((x), OHCI_TD_DI_MASK)
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#define OHCI_TD_SET_DI(x) __SHIFTIN((x), OHCI_TD_DI_MASK)
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#define OHCI_TD_NOINTR __SHIFTOUT_MASK(OHCI_TD_DI_MASK)
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#define OHCI_TD_TOGGLE_MASK __BITS(25,24) /* Toggle */
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#define OHCI_TD_GET_TOGGLE(x) __SHIFTOUT((x), OHCI_TD_TOGGLE_MASK)
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#define OHCI_TD_SET_TOGGLE(x) __SHIFTIN((x), OHCI_TD_TOGGLE_MASK)
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#define OHCI_TD_TOGGLE_CARRY 0
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#define OHCI_TD_TOGGLE_0 2
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#define OHCI_TD_TOGGLE_1 3
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#define OHCI_TD_EC_MASK __BITS(27,26) /* Error Count */
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#define OHCI_TD_GET_EC(x) __SHIFTOUT((x), OHCI_TD_EC_MASK)
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#define OHCI_TD_CC_MASK __BITS(31,28) /* Condition Code */
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#define OHCI_TD_GET_CC(x) __SHIFTOUT((x), OHCI_TD_CC_MASK)
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#define OHCI_TD_SET_CC(x) __SHIFTIN((x), OHCI_TD_CC_MASK)
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#define OHCI_TD_NOCC __SHIFTOUT_MASK(OHCI_TD_CC_MASK)
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volatile ohci_physaddr_t td_cbp; /* Current Buffer Pointer */
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volatile ohci_physaddr_t td_nexttd; /* Next TD */
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volatile ohci_physaddr_t td_be; /* Buffer End */
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} ohci_td_t;
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/* #define OHCI_TD_SIZE 16 */
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#define OHCI_TD_ALIGN 16
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#define OHCI_ITD_NOFFSET 8
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typedef struct {
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volatile uint32_t itd_flags;
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#define OHCI_ITD_SF_MASK __BITS(15,0)
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#define OHCI_ITD_GET_SF(x) __SHIFTOUT((x), OHCI_ITD_SF_MASK)
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#define OHCI_ITD_SET_SF(x) __SHIFTIN((x), OHCI_ITD_SF_MASK)
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#define OHCI_ITD_DI_MASK __BITS(23,21) /* Delay Interrupt */
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#define OHCI_ITD_GET_DI(x) __SHIFTOUT((x), OHCI_ITD_DI_MASK)
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#define OHCI_ITD_SET_DI(x) __SHIFTIN((x), OHCI_ITD_DI_MASK)
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#define OHCI_ITD_FC_MASK __BITS(26,24) /* Frame Count */
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#define OHCI_ITD_GET_FC(x) (__SHIFTOUT((x), OHCI_ITD_FC_MASK) + 1)
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#define OHCI_ITD_SET_FC(x) __SHIFTIN(((x) - 1), OHCI_ITD_FC_MASK)
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#define OHCI_ITD_CC_MASK __BITS(31,28) /* Condition Code */
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#define OHCI_ITD_GET_CC(x) __SHIFTOUT((x), OHCI_ITD_CC_MASK)
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#define OHCI_ITD_SET_CC(x) __SHIFTIN((x), OHCI_ITD_CC_MASK)
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#define OHCI_ITD_NOCC __SHIFTOUT_MASK(OHCI_ITD_CC_MASK)
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volatile ohci_physaddr_t itd_bp0; /* Buffer Page 0 */
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volatile ohci_physaddr_t itd_nextitd; /* Next ITD */
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volatile ohci_physaddr_t itd_be; /* Buffer End */
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volatile uint16_t itd_offset[OHCI_ITD_NOFFSET];/* Buffer offsets */
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#define itd_pswn itd_offset /* Packet Status Word*/
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#define OHCI_ITD_PAGE_SELECT __BIT(12)
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#define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff))
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#define OHCI_ITD_PSW_SIZE_MASK __BITS(10,0) /* Transfer length */
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#define OHCI_ITD_PSW_SIZE(x) __SHIFTOUT((x), OHCI_ITD_PSW_SIZE_MASK)
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#define OHCI_ITD_PSW_CC_MASK __BITS(15,12) /* Condition Code */
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#define OHCI_ITD_PSW_GET_CC(x) __SHIFTOUT((x), OHCI_ITD_PSW_CC_MASK)
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} ohci_itd_t;
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/* #define OHCI_ITD_SIZE 32 */
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#define OHCI_ITD_ALIGN 32
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#define OHCI_CC_NO_ERROR 0
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#define OHCI_CC_CRC 1
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#define OHCI_CC_BIT_STUFFING 2
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#define OHCI_CC_DATA_TOGGLE_MISMATCH 3
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#define OHCI_CC_STALL 4
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#define OHCI_CC_DEVICE_NOT_RESPONDING 5
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#define OHCI_CC_PID_CHECK_FAILURE 6
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#define OHCI_CC_UNEXPECTED_PID 7
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#define OHCI_CC_DATA_OVERRUN 8
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#define OHCI_CC_DATA_UNDERRUN 9
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#define OHCI_CC_BUFFER_OVERRUN 12
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#define OHCI_CC_BUFFER_UNDERRUN 13
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#define OHCI_CC_NOT_ACCESSED 14
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#define OHCI_CC_NOT_ACCESSED_MASK 14
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/* Some delay needed when changing certain registers. */
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#define OHCI_ENABLE_POWER_DELAY 5
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#define OHCI_READ_DESC_DELAY 5
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#endif /* _DEV_USB_OHCIREG_H_ */
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