172 lines
4.9 KiB
C
172 lines
4.9 KiB
C
/* $NetBSD: dcareg.h,v 1.7 2003/08/07 16:27:26 agc Exp $ */
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/*
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* Copyright (c) 1982, 1986, 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)dcareg.h 8.1 (Berkeley) 6/10/93
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*/
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#include <hp300/dev/iotypes.h> /* XXX */
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#ifdef hp700
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struct dcadevice {
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vu_char dca_reset;
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vu_char dca_pad[0x800-1];
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vu_char dca_data; /* receive buf or xmit hold */
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vu_char dca_ier; /* interrupt enable */
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vu_char dca_iir; /* (RO) interrupt identify */
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#define dca_fifo dca_iir /* (WO) FIFO control */
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vu_char dca_cfcr; /* line control */
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vu_char dca_mcr; /* modem control */
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vu_char dca_lsr; /* line status */
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vu_char dca_msr; /* modem status */
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vu_char dca_scr; /* scratch pad */
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};
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#else
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struct dcadevice {
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/* card registers */
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u_char dca_pad0;
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vu_char dca_id; /* 0x01 (read) */
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#define dca_reset dca_id /* 0x01 (write) */
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u_char dca_pad1;
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vu_char dca_ic; /* 0x03 */
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u_char dca_pad2;
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vu_char dca_ocbrc; /* 0x05 */
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u_char dca_pad3;
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vu_char dca_lcsm; /* 0x07 */
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u_char dca_pad4[8];
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/* chip registers */
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u_char dca_pad5;
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vu_char dca_data; /* 0x11 */
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u_char dca_pad6;
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vu_char dca_ier; /* 0x13 */
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u_char dca_pad7;
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vu_char dca_iir; /* 0x15 (read) */
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#define dca_fifo dca_iir /* 0x15 (write) */
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u_char dca_pad8;
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vu_char dca_cfcr; /* 0x17 */
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u_char dca_pad9;
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vu_char dca_mcr; /* 0x19 */
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u_char dca_padA;
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vu_char dca_lsr; /* 0x1B */
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u_char dca_padB;
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vu_char dca_msr; /* 0x1D */
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};
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#endif
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/* interface reset/id (300 only) */
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#define DCAID0 0x02
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#define DCAREMID0 0x82
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#define DCAID1 0x42
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#define DCAREMID1 0xC2
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/* interrupt control (300 only) */
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#define DCAIPL(x) ((((x) >> 4) & 3) + 3)
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#define IC_IR 0x40
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#define IC_IE 0x80
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/*
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* 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier)
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* NB: This constant is for a 7.3728 clock frequency. The 300 clock
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* frequency is 2.4576, giving a constant of 153600.
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*/
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#ifdef hp300
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#define DCABRD(x) (153600 / (x))
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#endif
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#ifdef hp700
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#define DCABRD(x) (460800 / (x))
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#endif
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/* interrupt enable register */
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#define IER_ERXRDY 0x1
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#define IER_ETXRDY 0x2
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#define IER_ERLS 0x4
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#define IER_EMSC 0x8
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/* interrupt identification register */
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#define IIR_IMASK 0xf
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#define IIR_RXTOUT 0xc
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#define IIR_RLS 0x6
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#define IIR_RXRDY 0x4
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#define IIR_TXRDY 0x2
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#define IIR_NOPEND 0x1
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#define IIR_MLSC 0x0
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#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
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/* fifo control register */
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#define FIFO_ENABLE 0x01
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#define FIFO_RCV_RST 0x02
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#define FIFO_XMT_RST 0x04
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#define FIFO_DMA_MODE 0x08
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#define FIFO_TRIGGER_1 0x00
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#define FIFO_TRIGGER_4 0x40
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#define FIFO_TRIGGER_8 0x80
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#define FIFO_TRIGGER_14 0xc0
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/* character format control register */
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#define CFCR_DLAB 0x80
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#define CFCR_SBREAK 0x40
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#define CFCR_PZERO 0x30
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#define CFCR_PONE 0x20
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#define CFCR_PEVEN 0x10
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#define CFCR_PODD 0x00
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#define CFCR_PENAB 0x08
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#define CFCR_STOPB 0x04
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#define CFCR_8BITS 0x03
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#define CFCR_7BITS 0x02
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#define CFCR_6BITS 0x01
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#define CFCR_5BITS 0x00
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/* modem control register */
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#define MCR_LOOPBACK 0x10
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#define MCR_IEN 0x08
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#define MCR_DRS 0x04
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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/* line status register */
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#define LSR_RCV_FIFO 0x80
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#define LSR_TSRE 0x40
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#define LSR_TXRDY 0x20
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#define LSR_BI 0x10
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#define LSR_FE 0x08
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#define LSR_PE 0x04
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#define LSR_OE 0x02
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#define LSR_RXRDY 0x01
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#define LSR_RCV_MASK 0x1f
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/* modem status register */
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#define MSR_DCD 0x80
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#define MSR_RI 0x40
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#define MSR_DSR 0x20
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#define MSR_CTS 0x10
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#define MSR_DDCD 0x08
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#define MSR_TERI 0x04
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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