483 lines
13 KiB
C
483 lines
13 KiB
C
/* $NetBSD: amdtemp.c,v 1.8 2009/06/16 07:34:40 cegger Exp $ */
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/* $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $ */
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/*
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Christoph Egger.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2008 Constantine A. Murenin <cnst+openbsd@bugmail.mojo.ru>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.8 2009/06/16 07:34:40 cegger Exp $ ");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kmem.h>
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#include <dev/sysmon/sysmonvar.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <machine/specialreg.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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/*
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* AMD K8:
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
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* AMD K8 Errata: #141
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* http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf
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*
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* Family10h:
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF
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*
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* Family11h:
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41256.pdf
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*/
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/* AMD Proessors, Function 3 -- Miscellaneous Control
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*/
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/* Function 3 Registers */
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#define THERMTRIP_STAT_R 0xe4
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#define NORTHBRIDGE_CAP_R 0xe8
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#define CPUID_FAMILY_MODEL_R 0xfc
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/*
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* AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control
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*/
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/* Bits within Thermtrip Status Register */
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#define K8_THERM_SENSE_SEL (1 << 6)
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#define K8_THERM_SENSE_CORE_SEL (1 << 2)
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/* Flip core and sensor selection bits */
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#define K8_T_SEL_C0(v) (v |= K8_THERM_SENSE_CORE_SEL)
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#define K8_T_SEL_C1(v) (v &= ~(K8_THERM_SENSE_CORE_SEL))
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#define K8_T_SEL_S0(v) (v &= ~(K8_THERM_SENSE_SEL))
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#define K8_T_SEL_S1(v) (v |= K8_THERM_SENSE_SEL)
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/*
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* AMD Family 10h Processorcs, Function 3 -- Miscellaneous Control
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*/
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/* Function 3 Registers */
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#define F10_TEMPERATURE_CTL_R 0xa4
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/* Bits within Reported Temperature Control Register */
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#define F10_TEMP_CURTEMP (1 << 21)
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/*
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* Revision Guide for AMD NPT Family 0Fh Processors,
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* Publication # 33610, Revision 3.30, February 2008
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*/
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#define K8_SOCKET_F 1 /* Server */
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#define K8_SOCKET_AM2 2 /* Desktop */
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#define K8_SOCKET_S1 3 /* Laptop */
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static const struct {
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const char rev[5];
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const struct {
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const pcireg_t cpuid;
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const uint8_t socket;
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} cpu[5];
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} amdtemp_core[] = {
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{ "BH-F", { { 0x00040FB0, K8_SOCKET_AM2 }, /* F2 */
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{ 0x00040F80, K8_SOCKET_S1 }, /* F2 */
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{ 0, 0 }, { 0, 0 }, { 0, 0 } } },
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{ "DH-F", { { 0x00040FF0, K8_SOCKET_AM2 }, /* F2 */
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{ 0x00040FC0, K8_SOCKET_S1 }, /* F2 */
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{ 0x00050FF0, K8_SOCKET_AM2 }, /* F2, F3 */
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{ 0, 0 }, { 0, 0 } } },
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{ "JH-F", { { 0x00040F10, K8_SOCKET_F }, /* F2, F3 */
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{ 0x00040F30, K8_SOCKET_AM2 }, /* F2, F3 */
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{ 0x000C0F10, K8_SOCKET_F }, /* F3 */
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{ 0, 0 }, { 0, 0 } } },
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{ "BH-G", { { 0x00060FB0, K8_SOCKET_AM2 }, /* G1, G2 */
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{ 0x00060F80, K8_SOCKET_S1 }, /* G1, G2 */
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{ 0, 0 }, { 0, 0 }, { 0, 0 } } },
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{ "DH-G", { { 0x00060FF0, K8_SOCKET_AM2 }, /* G1, G2 */
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{ 0x00060FC0, K8_SOCKET_S1 }, /* G2 */
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{ 0x00070FF0, K8_SOCKET_AM2 }, /* G1, G2 */
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{ 0x00070FC0, K8_SOCKET_S1 }, /* G2 */
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{ 0, 0 } } }
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};
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struct amdtemp_softc {
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_pcitag;
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struct sysmon_envsys *sc_sme;
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envsys_data_t *sc_sensor;
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char sc_rev;
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int8_t sc_numsensors;
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uint32_t sc_family;
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int32_t sc_adjustment;
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};
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static int amdtemp_match(device_t, cfdata_t, void *);
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static void amdtemp_attach(device_t, device_t, void *);
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static void amdtemp_k8_init(struct amdtemp_softc *, pcireg_t);
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static void amdtemp_k8_setup_sensors(struct amdtemp_softc *, int);
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static void amdtemp_k8_refresh(struct sysmon_envsys *, envsys_data_t *);
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static void amdtemp_family10_init(struct amdtemp_softc *);
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static void amdtemp_family10_setup_sensors(struct amdtemp_softc *, int);
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static void amdtemp_family10_refresh(struct sysmon_envsys *, envsys_data_t *);
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CFATTACH_DECL_NEW(amdtemp, sizeof(struct amdtemp_softc),
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amdtemp_match, amdtemp_attach, NULL, NULL);
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static int
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amdtemp_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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pcireg_t cpu_signature;
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uint32_t family;
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD)
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return 0;
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_AMD_AMD64_MISC:
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case PCI_PRODUCT_AMD_AMD64_F10_MISC:
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case PCI_PRODUCT_AMD_AMD64_F11_MISC:
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break;
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default:
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return 0;
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}
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cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag,
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CPUID_FAMILY_MODEL_R);
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/* This CPUID northbridge register has been introduced
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* in Revision F */
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if (cpu_signature == 0x0)
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return 0;
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family = CPUID2FAMILY(cpu_signature);
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if (family == 0xf)
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family += CPUID2EXTFAMILY(cpu_signature);
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/* Not yet supported CPUs */
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if (family >= 0x12)
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return 0;
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return 2; /* supercede pchb(4) */
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}
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static void
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amdtemp_attach(device_t parent, device_t self, void *aux)
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{
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struct amdtemp_softc *sc = device_private(self);
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struct pci_attach_args *pa = aux;
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pcireg_t cpu_signature;
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size_t len;
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int error;
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uint8_t i;
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aprint_naive("\n");
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aprint_normal(": AMD CPU Temperature Sensors");
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cpu_signature = pci_conf_read(pa->pa_pc, pa->pa_tag,
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CPUID_FAMILY_MODEL_R);
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/* If we hit this, then match routine is wrong. */
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KASSERT(cpu_signature != 0x0);
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sc->sc_family = CPUID2FAMILY(cpu_signature)
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+ CPUID2EXTFAMILY(cpu_signature);
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KASSERT(sc->sc_family >= 0xf);
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sc->sc_pc = pa->pa_pc;
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sc->sc_pcitag = pa->pa_tag;
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sc->sc_adjustment = 0;
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switch (sc->sc_family) {
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case 0xf: /* AMD K8 NPT */
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amdtemp_k8_init(sc, cpu_signature);
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break;
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case 0x10: /* AMD Barcelona/Phenom */
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case 0x11: /* AMD Griffin */
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amdtemp_family10_init(sc);
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break;
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default:
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aprint_normal(", family 0x%x not supported\n",
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sc->sc_family);
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return;
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}
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aprint_normal("\n");
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if (sc->sc_adjustment != 0)
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aprint_debug_dev(self, "Workaround enabled\n");
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sc->sc_sme = sysmon_envsys_create();
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len = sizeof(envsys_data_t) * sc->sc_numsensors;
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sc->sc_sensor = kmem_zalloc(len, KM_NOSLEEP);
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if (!sc->sc_sensor)
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goto bad2;
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switch (sc->sc_family) {
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case 0xf:
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amdtemp_k8_setup_sensors(sc, device_unit(self));
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break;
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case 0x10:
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case 0x11:
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amdtemp_family10_setup_sensors(sc, device_unit(self));
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break;
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}
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/*
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* Set properties in sensors.
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*/
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for (i = 0; i < sc->sc_numsensors; i++) {
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if (sysmon_envsys_sensor_attach(sc->sc_sme,
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&sc->sc_sensor[i]))
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goto bad;
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}
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/*
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* Register the sysmon_envsys device.
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*/
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sc->sc_sme->sme_name = device_xname(self);
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sc->sc_sme->sme_cookie = sc;
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switch (sc->sc_family) {
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case 0xf:
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sc->sc_sme->sme_refresh = amdtemp_k8_refresh;
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break;
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case 0x10:
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case 0x11:
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sc->sc_sme->sme_refresh = amdtemp_family10_refresh;
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break;
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}
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error = sysmon_envsys_register(sc->sc_sme);
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if (error) {
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aprint_error_dev(self, "unable to register with sysmon "
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"(error=%d)\n", error);
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goto bad;
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}
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if (!pmf_device_register(self, NULL, NULL))
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aprint_error_dev(self, "couldn't establish power handler\n");
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return;
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bad:
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kmem_free(sc->sc_sensor, len);
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bad2:
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sysmon_envsys_destroy(sc->sc_sme);
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}
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static void
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amdtemp_k8_init(struct amdtemp_softc *sc, pcireg_t cpu_signature)
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{
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pcireg_t data;
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uint32_t cmpcap;
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uint8_t i, j;
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aprint_normal(" (K8");
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for (i = 0; i < __arraycount(amdtemp_core) && sc->sc_rev == '\0'; i++) {
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for (j = 0; amdtemp_core[i].cpu[j].cpuid != 0; j++) {
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if ((cpu_signature & ~0xf)
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!= amdtemp_core[i].cpu[j].cpuid)
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continue;
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sc->sc_rev = amdtemp_core[i].rev[3];
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aprint_normal(": core rev %.4s%.1x",
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amdtemp_core[i].rev,
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CPUID2STEPPING(cpu_signature));
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switch (amdtemp_core[i].cpu[j].socket) {
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case K8_SOCKET_AM2:
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if (sc->sc_rev == 'G')
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sc->sc_adjustment = 21000000;
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aprint_normal(", socket AM2");
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break;
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case K8_SOCKET_S1:
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aprint_normal(", socket S1");
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break;
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case K8_SOCKET_F:
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aprint_normal(", socket F");
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break;
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}
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}
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}
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if (sc->sc_rev == '\0') {
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/* CPUID Family Model Register was introduced in
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* Revision F */
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sc->sc_rev = 'G'; /* newer than E, assume G */
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aprint_normal(": cpuid 0x%x", cpu_signature);
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}
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aprint_normal(")");
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data = pci_conf_read(sc->sc_pc, sc->sc_pcitag, NORTHBRIDGE_CAP_R);
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cmpcap = (data >> 12) & 0x3;
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sc->sc_numsensors = cmpcap ? 4 : 2;
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}
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static void
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amdtemp_k8_setup_sensors(struct amdtemp_softc *sc, int dv_unit)
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{
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uint8_t i;
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/* There are two sensors per CPU core. So we use the
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* device unit as socket counter to correctly enumerate
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* the CPUs on multi-socket machines.
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*/
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dv_unit *= (sc->sc_numsensors / 2);
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for (i = 0; i < sc->sc_numsensors; i++) {
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sc->sc_sensor[i].units = ENVSYS_STEMP;
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sc->sc_sensor[i].state = ENVSYS_SVALID;
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snprintf(sc->sc_sensor[i].desc, sizeof(sc->sc_sensor[i].desc),
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"CPU%u Sensor%u", dv_unit + (i / 2), i % 2);
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}
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}
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static void
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amdtemp_k8_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
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{
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struct amdtemp_softc *sc = sme->sme_cookie;
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pcireg_t status, match, tmp;
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uint32_t value;
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status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R);
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switch(edata->sensor) { /* sensor number */
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case 0: /* Core 0 Sensor 0 */
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K8_T_SEL_C0(status);
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K8_T_SEL_S0(status);
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break;
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case 1: /* Core 0 Sensor 1 */
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K8_T_SEL_C0(status);
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K8_T_SEL_S1(status);
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break;
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case 2: /* Core 1 Sensor 0 */
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K8_T_SEL_C1(status);
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K8_T_SEL_S0(status);
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break;
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case 3: /* Core 1 Sensor 1 */
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K8_T_SEL_C1(status);
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K8_T_SEL_S1(status);
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break;
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}
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match = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL);
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pci_conf_write(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R, status);
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status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, THERMTRIP_STAT_R);
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tmp = status & (K8_THERM_SENSE_CORE_SEL | K8_THERM_SENSE_SEL);
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value = 0x3ff & (status >> 14);
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if (sc->sc_rev != 'G')
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value &= ~0x3;
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edata->state = ENVSYS_SINVALID;
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if ((tmp == match) && ((value & ~0x3) != 0)) {
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edata->state = ENVSYS_SVALID;
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edata->value_cur = (value * 250000 - 49000000) + 273150000
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+ sc->sc_adjustment;
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}
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}
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static void
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amdtemp_family10_init(struct amdtemp_softc *sc)
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{
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aprint_normal(" (Family10h / Family11h)");
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sc->sc_numsensors = 1;
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}
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static void
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amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit)
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{
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/* sanity check for future enhancements */
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KASSERT(sc->sc_numsensors == 1);
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/* There's one sensor per memory controller (= socket)
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* so we use the device unit as socket counter
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* to correctly enumerate the CPUs
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*/
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sc->sc_sensor[0].units = ENVSYS_STEMP;
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sc->sc_sensor[0].state = ENVSYS_SVALID;
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snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc),
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"CPU%u Sensor0", dv_unit);
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}
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static void
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amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
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{
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struct amdtemp_softc *sc = sme->sme_cookie;
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pcireg_t status;
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uint32_t value;
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status = pci_conf_read(sc->sc_pc, sc->sc_pcitag, F10_TEMPERATURE_CTL_R);
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value = (status >> 21);
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edata->state = ENVSYS_SVALID;
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|
/* envsys(4) wants uK... convert from Celsius. */
|
|
edata->value_cur = (value * 125000) + 273150000;
|
|
}
|