292 lines
7.0 KiB
C
292 lines
7.0 KiB
C
/* $NetBSD: pci_machdep.c,v 1.27 2008/05/30 19:26:35 ad Exp $ */
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/*
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* Copyright (c) 2000 Soren S. Jorvang. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.27 2008/05/30 19:26:35 ad Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#define _COBALT_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciconf.h>
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#include <dev/pci/pciide_apollo_reg.h>
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#include <cobalt/dev/gtreg.h>
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/*
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* PCI doesn't have any special needs; just use
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* the generic versions of these functions.
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*/
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struct cobalt_bus_dma_tag pci_bus_dma_tag = {
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_bus_dmamap_create,
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_bus_dmamap_destroy,
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_bus_dmamap_load,
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_bus_dmamap_load_mbuf,
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_bus_dmamap_load_uio,
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_bus_dmamap_load_raw,
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_bus_dmamap_unload,
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_bus_dmamap_sync,
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_bus_dmamem_alloc,
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_bus_dmamem_free,
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_bus_dmamem_map,
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_bus_dmamem_unmap,
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_bus_dmamem_mmap,
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};
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void
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pci_attach_hook(struct device *parent, struct device *self,
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struct pcibus_attach_args *pba)
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{
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/* XXX */
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return;
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}
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int
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pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
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{
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return 32;
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}
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pcitag_t
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pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
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{
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return (bus << 16) | (device << 11) | (function << 8);
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}
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void
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pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x07;
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}
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pcireg_t
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pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
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{
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pcireg_t data;
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int bus, dev, func;
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pci_decompose_tag(pc, tag, &bus, &dev, &func);
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/*
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* 2700 hardware wedges on accesses to device 6.
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*/
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if (bus == 0 && dev == 6)
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return 0;
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/*
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* 2800 hardware wedges on accesses to device 31.
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*/
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if (bus == 0 && dev == 31)
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return 0;
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bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR,
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PCICFG_ENABLE | tag | reg);
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data = bus_space_read_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_DATA);
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bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR, 0);
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return data;
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}
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void
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pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
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{
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bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR,
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PCICFG_ENABLE | tag | reg);
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bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_DATA, data);
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bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR, 0);
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}
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int
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pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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pci_chipset_tag_t pc = pa->pa_pc;
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pcitag_t intrtag = pa->pa_intrtag;
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int pin = pa->pa_intrpin;
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int line = pa->pa_intrline;
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int bus, dev, func;
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pci_decompose_tag(pc, intrtag, &bus, &dev, &func);
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/*
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* The interrupt lines of the internal Tulips are connected
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* directly to the CPU.
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*/
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if (cobalt_id == COBALT_ID_QUBE2700) {
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if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A) {
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/* tulip is connected to CPU INT2 on Qube2700 */
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*ihp = NICU_INT + 2;
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return 0;
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}
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} else {
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if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A) {
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/* the primary tulip is connected to CPU INT1 */
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*ihp = NICU_INT + 1;
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return 0;
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}
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if (bus == 0 && dev == 12 && pin == PCI_INTERRUPT_PIN_A) {
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/* the secondary tulip is connected to CPU INT2 */
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*ihp = NICU_INT + 2;
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return 0;
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}
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}
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/* sanity check */
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if (line == 0 || line >= NICU_INT)
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return -1;
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*ihp = line;
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return 0;
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}
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const char *
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pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
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{
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static char irqstr[8];
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if (ih >= NICU_INT)
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sprintf(irqstr, "level %d", ih - NICU_INT);
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else
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sprintf(irqstr, "irq %d", ih);
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return irqstr;
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}
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const struct evcnt *
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pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
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{
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/* XXX for now, no evcnt parent reported */
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return NULL;
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}
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int
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pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
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int attr, uint64_t data)
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{
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switch (attr) {
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case PCI_INTR_MPSAFE:
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return 0;
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default:
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return ENODEV;
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}
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}
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void *
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pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
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int (*func)(void *), void *arg)
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{
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if (ih >= NICU_INT)
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return cpu_intr_establish(ih - NICU_INT, level, func, arg);
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else
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return icu_intr_establish(ih, IST_LEVEL, level, func, arg);
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}
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void
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pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
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{
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/* Try both, only the valid one will disestablish. */
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cpu_intr_disestablish(cookie);
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icu_intr_disestablish(cookie);
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}
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void
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pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz,
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int *iline)
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{
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/*
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* Use irq 9 on all devices on the Qube's PCI slot.
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* XXX doesn't handle devices over PCI-PCI bridges
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*/
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if (bus == 0 && dev == 10 && pin != PCI_INTERRUPT_PIN_NONE)
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*iline = 9;
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}
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int
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pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
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{
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/* ignore bogus IDs */
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if (PCI_VENDOR(id) == 0)
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return 0;
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/* 2700 hardware wedges on accesses to device 6. */
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if (bus == 0 && dev == 6)
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return 0;
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/* 2800 hardware wedges on accesses to device 31. */
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if (bus == 0 && dev == 31)
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return 0;
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/* Don't configure the bridge and PCI probe. */
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if (PCI_VENDOR(id) == PCI_VENDOR_MARVELL &&
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PCI_PRODUCT(id) == PCI_PRODUCT_MARVELL_GT64011)
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return 0;
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/* Don't configure on-board VIA VT82C586 (pcib, uhci) */
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if (bus == 0 && dev == 9 && (func == 0 || func == 2))
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return 0;
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/* Enable viaide secondary port. Some firmware doesn't enable it. */
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if (bus == 0 && dev == 9 && func == 1) {
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pcitag_t tag;
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pcireg_t csr;
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#define APO_VIAIDECONF (APO_VIA_REGBASE + 0x00)
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tag = pci_make_tag(pc, bus, dev, func);
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csr = pci_conf_read(pc, tag, APO_VIAIDECONF);
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pci_conf_write(pc, tag, APO_VIAIDECONF,
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csr | APO_IDECONF_EN(1));
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}
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return PCI_CONF_DEFAULT & ~(PCI_COMMAND_SERR_ENABLE |
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PCI_COMMAND_PARITY_ENABLE);
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}
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