139 lines
4.3 KiB
C
139 lines
4.3 KiB
C
/* $NetBSD: dz_uba.c,v 1.8 2000/01/24 02:40:29 matt Exp $ */
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/*
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* Copyright (c) 1998 Ludd, University of Lule}, Sweden. All rights reserved.
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* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed at Ludd, University of
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* Lule}, Sweden and its contributors.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ioctl.h>
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#include <sys/tty.h>
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#include <sys/proc.h>
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#include <sys/map.h>
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#include <sys/buf.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/uio.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <machine/pte.h>
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#include <machine/trap.h>
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#include <machine/scb.h>
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#include <dev/qbus/ubavar.h>
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#include <dev/qbus/dzreg.h>
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#include <dev/qbus/dzvar.h>
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#include "ioconf.h"
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static int dz_uba_match __P((struct device *, struct cfdata *, void *));
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static void dz_uba_attach __P((struct device *, struct device *, void *));
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struct cfattach dz_uba_ca = {
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sizeof(struct dz_softc), dz_uba_match, dz_uba_attach
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};
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/* Autoconfig handles: setup the controller to interrupt, */
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/* then complete the housecleaning for full operation */
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static int
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dz_uba_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct uba_attach_args *ua = aux;
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bus_space_tag_t iot = ua->ua_iot;
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bus_space_handle_t ioh = ua->ua_ioh;
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register int n;
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iot = iot; /* Silly GCC */
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/* Reset controller to initialize, enable TX interrupts */
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/* to catch floating vector info elsewhere when completed */
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bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_MSE | DZ_CSR_TXIE);
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bus_space_write_1(iot, ioh, DZ_UBA_TCR, 1);
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DELAY(100000); /* delay 1/10 second */
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bus_space_write_2(iot, ioh, DZ_UBA_CSR, DZ_CSR_RESET);
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/* Now wait up to 3 seconds for reset/clear to complete. */
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for (n = 0; n < 300; n++) {
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DELAY(10000);
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if ((bus_space_read_2(iot, ioh, DZ_UBA_CSR)&DZ_CSR_RESET) == 0)
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break;
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}
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/* If the RESET did not clear after 3 seconds, */
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/* the controller must be broken. */
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if (n >= 300)
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return (0);
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/* Register the TX interrupt handler */
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return (1);
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}
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static void
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dz_uba_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct dz_softc *sc = (void *)self;
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register struct uba_attach_args *ua = aux;
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sc->sc_iot = ua->ua_iot;
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sc->sc_ioh = ua->ua_ioh;
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sc->sc_dr.dr_csr = DZ_UBA_CSR;
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sc->sc_dr.dr_rbuf = DZ_UBA_RBUF;
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sc->sc_dr.dr_dtr = DZ_UBA_DTR;
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sc->sc_dr.dr_break = DZ_UBA_BREAK;
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sc->sc_dr.dr_tbuf = DZ_UBA_TBUF;
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sc->sc_dr.dr_tcr = DZ_UBA_TCR;
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sc->sc_dr.dr_dcd = DZ_UBA_DCD;
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sc->sc_dr.dr_ring = DZ_UBA_RING;
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sc->sc_type = DZ_DZ;
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/* Now register the TX & RX interrupt handlers */
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uba_intr_establish(ua->ua_icookie, ua->ua_cvec, dzxint, sc);
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uba_intr_establish(ua->ua_icookie, ua->ua_cvec - 4, dzrint, sc);
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dzattach(sc);
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}
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