491 lines
15 KiB
C
491 lines
15 KiB
C
/* $NetBSD: bhareg.h,v 1.20 2008/04/28 20:23:49 martin Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
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* Simulation Facility, NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Originally written by Julian Elischer (julian@tfs.com)
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* for TRW Financial Systems for use under the MACH(2.5) operating system.
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*
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* TRW Financial Systems, in accordance with their agreement with Carnegie
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* Mellon University, makes this software available to CMU to distribute
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* or use in any manner that they see fit as long as this message is kept with
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* the software. For this reason TFS also grants any other persons or
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* organisations permission to use or modify this software.
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*
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* TFS supplies this software to be publicly redistributed
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* on the understanding that TFS is not responsible for the correct
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* functioning of this software in any circumstances.
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*/
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typedef u_int8_t physaddr[4];
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typedef u_int8_t physlen[4];
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#define ltophys _lto4l
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#define phystol _4ltol
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/*
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* I/O port offsets
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*/
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#define BHA_CTRL_PORT 0 /* control (wo) */
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#define BHA_STAT_PORT 0 /* status (ro) */
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#define BHA_CMD_PORT 1 /* command (wo) */
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#define BHA_DATA_PORT 1 /* data (ro) */
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#define BHA_INTR_PORT 2 /* interrupt status (ro) */
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#define BHA_EXTGEOM_PORT 3 /* extended geometry (ro) */
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/*
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* BHA_CTRL bits
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*/
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#define BHA_CTRL_HRST 0x80 /* Hardware reset */
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#define BHA_CTRL_SRST 0x40 /* Software reset */
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#define BHA_CTRL_IRST 0x20 /* Interrupt reset */
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#define BHA_CTRL_SCRST 0x10 /* SCSI bus reset */
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/*
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* BHA_STAT bits
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*/
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#define BHA_STAT_STST 0x80 /* Self test in Progress */
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#define BHA_STAT_DIAGF 0x40 /* Diagnostic Failure */
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#define BHA_STAT_INIT 0x20 /* Mbx Init required */
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#define BHA_STAT_IDLE 0x10 /* Host Adapter Idle */
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#define BHA_STAT_CDF 0x08 /* cmd/data out port full */
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#define BHA_STAT_DF 0x04 /* Data in port full */
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#define BHA_STAT_INVDCMD 0x01 /* Invalid command */
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/*
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* BHA_CMD opcodes
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*/
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#define BHA_NOP 0x00 /* No operation */
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#define BHA_MBX_INIT 0x01 /* Mbx initialization */
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#define BHA_START_SCSI 0x02 /* start scsi command */
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#define BHA_EXECUTE_BIOS_CMD 0x03 /* execute BIOS command */
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#define BHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */
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#define BHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */
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#define BHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */
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#define BHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */
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#define BHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */
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#define BHA_BUS_SPEED_SET 0x09 /* set bus transfer speed */
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#define BHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */
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#define BHA_INQUIRE_CONFIG 0x0b /* return configuration data */
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#define BHA_TARGET_EN 0x0c /* enable target mode */
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#define BHA_INQUIRE_SETUP 0x0d /* return setup data */
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#define BHA_WRITE_LRAM 0x1a /* write adapter local RAM */
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#define BHA_READ_LRAM 0x1b /* read adapter local RAM */
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#define BHA_WRITE_CHIP_FIFO 0x1c /* write bus master chip FIFO */
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#define BHA_READ_CHIP_FIFO 0x1d /* read bus master chip FIFO */
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#define BHA_ECHO 0x1f /* Echo command byte */
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#define BHA_ADAPTER_DIAGNOSTICS 0x20 /* host adapter diagnostics */
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#define BHA_SET_ADAPTER_OPTIONS 0x21 /* set adapter options */
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#define BHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */
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#define BHA_INQUIRE_TARG_DEVS 0x24 /* inquire target devices */
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#define BHA_DISABLE_HAC_INTR 0x25 /* disable host adapter interrupt */
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#define BHA_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */
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#define BHA_EXECUTE_SCSI_CMD 0x83 /* execute SCSI command */
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#define BHA_INQUIRE_REVISION_3 0x84 /* Get 3rd firmware version byte */
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#define BHA_INQUIRE_REVISION_4 0x85 /* Get 4th firmware version byte */
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#define BHA_INQUIRE_PCI_INFO 0x86 /* get PCI host adapter information */
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#define BHA_INQUIRE_MODEL 0x8b /* Get hardware ID and revision */
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#define BHA_INQUIRE_PERIOD 0x8c /* Get synchronous period */
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#define BHA_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */
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#define BHA_ROUND_ROBIN 0x8f /* Enable/Disable(default)
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round robin */
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#define BHA_STORE_LRAM 0x90 /* store host adapter local RAM */
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#define BHA_FETCH_LRAM 0x91 /* fetch host adapter local RAM */
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#define BHA_SAVE_TO_EEPROM 0x92 /* store local RAM data in EEPROM */
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#define BHA_UPLOAD_AUTOSCSI 0x94 /* upload AutoSCSI code */
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#define BHA_MODIFY_IOPORT 0x95 /* change or disable I/O port */
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#define BHA_SET_CCB_FORMAT 0x96 /* set CCB format (legacy/wide lun) */
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#define BHA_WRITE_INQUIRY_BUF 0x9a /* write inquiry buffer */
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#define BHA_READ_INQUIRY_BUF 0x9b /* read inquiry buffer */
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#define BHA_FLASH_UP_DOWNLOAD 0xa7 /* flash upload/downlod */
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#define BHA_READ_SCAM_DATA 0xa8 /* read SCAM data */
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#define BHA_WRITE_SCAM_DATA 0xa9 /* write SCAM data */
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/*
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* BHA_INTR bits
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*/
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#define BHA_INTR_ANYINTR 0x80 /* Any interrupt */
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#define BHA_INTR_SCRD 0x08 /* SCSI reset detected */
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#define BHA_INTR_HACC 0x04 /* Command complete */
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#define BHA_INTR_MBOA 0x02 /* MBX out empty */
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#define BHA_INTR_MBIF 0x01 /* MBX in full */
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struct bha_mbx_out {
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physaddr ccb_addr;
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u_int8_t reserved[3];
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u_int8_t cmd;
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};
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struct bha_mbx_in {
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physaddr ccb_addr;
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u_int8_t host_stat;
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u_int8_t target_stat;
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u_int8_t reserved;
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u_int8_t comp_stat;
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};
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/*
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* mbo.cmd values
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*/
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#define BHA_MBO_FREE 0x0 /* MBO entry is free */
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#define BHA_MBO_START 0x1 /* MBO activate entry */
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#define BHA_MBO_ABORT 0x2 /* MBO abort entry */
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/*
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* mbi.comp_stat values
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*/
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#define BHA_MBI_FREE 0x0 /* MBI entry is free */
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#define BHA_MBI_OK 0x1 /* completed without error */
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#define BHA_MBI_ABORT 0x2 /* aborted ccb */
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#define BHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */
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#define BHA_MBI_ERROR 0x4 /* Completed with error */
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#if defined(BIG_DMA)
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WARNING...THIS WON'T WORK(won't fit on 1 page)
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#if 0
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#define BHA_NSEG 2048 /* Number of scatter gather segments - to much vm */
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#endif
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#define BHA_NSEG 128
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#else
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#define BHA_NSEG 33
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#endif /* BIG_DMA */
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struct bha_scat_gath {
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physlen seg_len;
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physaddr seg_addr;
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};
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struct bha_ccb {
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u_int8_t opcode;
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#if BYTE_ORDER == LITTLE_ENDIAN
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u_int8_t :3,
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data_in :1,
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data_out :1,
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wide_tag_enable :1, /* Wide Lun CCB format */
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wide_tag_type :2; /* Wide Lun CCB format */
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#else
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u_int8_t wide_tag_type :2, /* Wide Lun CCB format */
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wide_tag_enable :1, /* Wide Lun CCB format */
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data_out :1,
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data_in :1,
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:3;
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#endif
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u_int8_t scsi_cmd_length;
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u_int8_t req_sense_length;
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/*------------------------------------longword boundary */
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physlen data_length;
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/*------------------------------------longword boundary */
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physaddr data_addr;
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/*------------------------------------longword boundary */
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u_int8_t reserved1[2];
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u_int8_t host_stat;
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u_int8_t target_stat;
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/*------------------------------------longword boundary */
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u_int8_t target;
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#if BYTE_ORDER == LITTLE_ENDIAN
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u_int8_t lun :5,
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tag_enable :1,
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tag_type :2;
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#else
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u_int8_t tag_type :2,
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tag_enable :1,
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lun :5;
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#endif
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u_int8_t scsi_cmd[12];
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u_int8_t reserved2[1];
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u_int8_t link_id;
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/*------------------------------------longword boundary */
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physaddr link_addr;
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/*------------------------------------longword boundary */
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physaddr sense_ptr;
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/*-----end of HW fields-----------------------longword boundary */
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struct scsi_sense_data scsi_sense;
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/*------------------------------------longword boundary */
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struct bha_scat_gath scat_gath[BHA_NSEG];
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/*------------------------------------longword boundary */
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TAILQ_ENTRY(bha_ccb) chain;
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struct bha_ccb *nexthash;
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bus_addr_t hashkey;
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struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */
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int flags;
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#define CCB_ALLOC 0x01
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#define CCB_ABORT 0x02
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#ifdef BHADIAG
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#define CCB_SENDING 0x04
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#endif
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int timeout;
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/*
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* This DMA map maps the buffer involved in the transfer.
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* Its contents are loaded into "scat_gath" above.
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*/
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bus_dmamap_t dmamap_xfer;
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};
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/*
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* opcode fields
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*/
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#define BHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */
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#define BHA_TARGET_CCB 0x01 /* SCSI Target CCB */
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#define BHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with S/G */
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#define BHA_INIT_RESID_CCB 0x03 /* SCSI Initiator w/ residual */
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#define BHA_INIT_RESID_SG_CCB 0x04 /* SCSI Initiator w/ residual and S/G */
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#define BHA_RESET_CCB 0x81 /* SCSI Bus reset */
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/*
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* bha_ccb.host_stat values
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*/
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#define BHA_OK 0x00 /* cmd ok */
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#define BHA_LINK_OK 0x0a /* Link cmd ok */
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#define BHA_LINK_IT 0x0b /* Link cmd ok + int */
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#define BHA_DATA_UNDRN 0x0c /* data underrun error */
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#define BHA_SEL_TIMEOUT 0x11 /* Selection time out */
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#define BHA_OVER_UNDER 0x12 /* Data over/under run */
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#define BHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */
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#define BHA_INV_BUS 0x14 /* Invalid bus phase/sequence */
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#define BHA_BAD_MBO 0x15 /* Incorrect MBO cmd */
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#define BHA_BAD_CCB 0x16 /* Incorrect ccb opcode */
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#define BHA_BAD_LINK 0x17 /* Not same values of LUN for links */
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#define BHA_INV_TARGET 0x18 /* Invalid target direction */
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#define BHA_CCB_DUP 0x19 /* Duplicate CCB received */
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#define BHA_INV_CCB 0x1a /* Invalid CCB or segment list */
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#define BHA_AUTOSENSE_FAILED 0x1b /* auto REQUEST SENSE failed */
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#define BHA_TAGGED_MSG_REJ 0x1c /* tagged queueing message rejected */
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#define BHA_UNSUP_MSG_RECVD 0x1d /* unsupported message received */
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#define BHA_HARDWARE_FAILURE 0x20 /* host adapter hardware failure */
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#define BHA_TARG_IGNORED_ATN 0x21 /* target ignored ATN signal */
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#define BHA_HA_SCSI_BUS_RESET 0x22 /* host adapter asserted RST */
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#define BHA_OTHER_SCSI_BUS_RESET 0x23 /* other device asserted RST */
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#define BHA_BAD_RECONNECT 0x24 /* target reconnected improperly */
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#define BHA_HA_BUS_DEVICE_RESET 0x25 /* host adapter performed BDR */
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#define BHA_ABORT_QUEUE 0x26 /* abort queue generated */
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#define BHA_SOFTWARE_FAILURE 0x27 /* host adapter software failure */
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#define BHA_HARDWARE_WATCHDOG 0x30 /* host adapter watchdog timer fired */
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#define BHA_SCSI_PARITY_ERROR 0x34 /* SCSI parity error detected */
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struct bha_extended_inquire {
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struct {
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u_char opcode;
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u_char len;
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} cmd;
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struct {
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u_char bus_type; /* Type of bus connected to */
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#define BHA_BUS_TYPE_24BIT 'A' /* ISA bus */
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#define BHA_BUS_TYPE_32BIT 'E' /* EISA/VLB/PCI bus */
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#define BHA_BUS_TYPE_MCA 'M' /* MicroChannel bus */
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u_char bios_address; /* Address of adapter BIOS */
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u_short sg_limit;
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u_char mbox_count;
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u_char mbox_baseaddr[4]; /* packed/unaligned u_int32_t */
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u_char intrflags;
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#define BHA_INTR_FASTEISA 0x04
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#define BHA_INTR_LEVEL 0x40 /* bit 6: level-sensitive interrupt */
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u_char firmware_level[3]; /* last 3 digits of firmware rev */
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u_char scsi_flags; /* supported SCSI features */
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#define BHA_SCSI_WIDE 0x01 /* host adapter is wide */
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#define BHA_SCSI_DIFFERENTIAL 0x02 /* host adapter is differential */
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#define BHA_SCSI_SCAM 0x04 /* host adapter supports SCAM */
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#define BHA_SCSI_ULTRA 0x08 /* host adapter supports Ultra */
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#define BHA_SCSI_TERMINATION 0x10 /* host adapter supports smart
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termination */
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} reply;
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};
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struct bha_config {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char chan;
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u_char intr;
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#if BYTE_ORDER == LITTLE_ENDIAN
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u_char scsi_dev :3,
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:5;
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#else
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u_char :5,
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scsi_dev :3;
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#endif
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} reply;
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};
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struct bha_toggle {
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struct {
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u_char opcode;
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u_char enable;
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} cmd;
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};
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struct bha_mailbox {
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struct {
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u_char opcode;
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u_char nmbx;
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physaddr addr;
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} cmd;
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};
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struct bha_model {
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struct {
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u_char opcode;
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u_char len;
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} cmd;
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struct {
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u_char id[4]; /* i.e bt742a -> '7','4','2','A' */
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u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */
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} reply;
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};
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struct bha_revision {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char board_type;
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u_char custom_feature;
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char firm_revision;
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u_char firm_version;
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} reply;
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};
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struct bha_digit {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char digit;
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} reply;
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};
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struct bha_devices {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char lun_map[8];
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} reply;
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};
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struct bha_sync {
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#if BYTE_ORDER == LITTLE_ENDIAN
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u_char offset :4,
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period :3,
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valid :1;
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#else
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u_char valid :1,
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period :3,
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offset :4;
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#endif
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};
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struct bha_setup_reply {
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#if BYTE_ORDER == LITTLE_ENDIAN
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u_int8_t sync_neg :1,
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parity :1,
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:6;
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#else
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u_int8_t :6,
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parity :1,
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sync_neg :1;
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#endif
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u_int8_t speed;
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u_int8_t bus_on;
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u_int8_t bus_off;
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u_int8_t num_mbx;
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u_int8_t mbx[3]; /*XXX */
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/* doesn't make sense with 32bit addresses */
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struct bha_sync sync_low[8];
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u_int8_t low_disc_info;
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};
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/* additional reply data supplied by wide controllers */
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struct bha_setup_reply_wide {
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u_int8_t signature;
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u_int8_t letter_d;
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u_int8_t ha_type;
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u_int8_t low_wide_allowed;
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u_int8_t low_wide_active;
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struct bha_sync sync_high[8];
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u_int8_t high_disc_info;
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u_int8_t reserved;
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u_int8_t high_wide_allowed;
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u_int8_t high_wide_active;
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};
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struct bha_setup {
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struct {
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u_char opcode;
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u_char len;
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} cmd;
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struct bha_setup_reply reply;
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struct bha_setup_reply_wide reply_w; /* for wide controllers */
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};
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struct bha_period_reply {
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u_char period[8];
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};
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struct bha_period {
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struct {
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u_char opcode;
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|
u_char len;
|
|
} cmd;
|
|
struct bha_period_reply reply;
|
|
struct bha_period_reply reply_w; /* for wide controllers */
|
|
};
|
|
|
|
struct bha_isadisable {
|
|
struct {
|
|
u_char opcode;
|
|
u_char modifier;
|
|
} cmd;
|
|
};
|
|
|
|
/*
|
|
* bha_isadisable.modifier parameters
|
|
*/
|
|
#define BHA_IOMODIFY_330 0x00
|
|
#define BHA_IOMODIFY_334 0x01
|
|
#define BHA_IOMODIFY_DISABLE1 0x06
|
|
#define BHA_IOMODIFY_DISABLE2 0x07
|
|
|
|
#define INT9 0x01
|
|
#define INT10 0x02
|
|
#define INT11 0x04
|
|
#define INT12 0x08
|
|
#define INT14 0x20
|
|
#define INT15 0x40
|
|
|
|
#define EISADMA 0x00
|
|
#define CHAN0 0x01
|
|
#define CHAN5 0x20
|
|
#define CHAN6 0x40
|
|
#define CHAN7 0x80
|