232 lines
7.8 KiB
C
232 lines
7.8 KiB
C
/* $NetBSD: mgxreg.h,v 1.5 2017/07/29 03:29:49 macallan Exp $ */
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/* register definitions based on OpenBSD's atxxreg.h: */
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/*
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* Copyright (c) 2008 Miodrag Vallat.
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* Copyright (c) 2014 Michael Lorenz
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* Alliance Promotion AP6422, AT24 and AT3D extended register set definitions.
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*
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* This has been reconstructed from XFree86 ``apm'' driver, whose authors
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* apparently do not believe in meaningful constants for numbers. See
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* apm_regs.h for more madness.
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*/
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#ifndef MGX_REG_H
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#define MGX_REG_H
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#define VGA_BASE 0x3c0
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#define CRTC_INDEX 0x3d4
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#define CRTC_DATA 0x3d5
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#define SEQ_INDEX 0x3c4
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#define SEQ_DATA 0x3c5
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/*
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* some bits from the XFree86 3.x vga256 / apm driver:
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* - sequencer registers 0x11 - 0x17 contain the chip's ID, 'Pro6424' for AT24
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*/
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#define SEQ_APERTURE 0x1c
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#define AP_SIZE_MASK 0x06
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#define AP_SIZE_1MB 0x00
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#define AP_SIZE_2MB 0x02
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#define AP_SIZE_4MB 0x04
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#define AP_SIZE_6MB 0x06
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#define AP_SIMULTANEOUS 0x20 /* sim. access to VRAM? */
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/*
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* Clipping Control
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*/
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#define ATR_CLIP_CONTROL 0x0030 /* byte access */
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#define ATR_CLIP_LEFT 0x0038
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#define ATR_CLIP_TOP 0x003a
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#define ATR_CLIP_LEFTTOP 0x0038
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#define ATR_CLIP_RIGHT 0x003c
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#define ATR_CLIP_BOTTOM 0x003e
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#define ATR_CLIP_RIGHTBOTTOM 0x003c
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/*
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* Drawing Engine
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*/
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#define ATR_DEC 0x0040
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#define ATR_ROP 0x0046
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#define ATR_BYTEMASK 0x0047
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#define ATR_PATTERN1 0x0048
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#define ATR_PATTERN2 0x004c
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#define ATR_SRC_X 0x0050
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#define ATR_SRC_Y 0x0052
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#define ATR_SRC_XY 0x0050 /* pointer in vram if DEC_SRC_LINEAR */
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#define ATR_DST_X 0x0054
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#define ATR_DST_Y 0x0056
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#define ATR_DST_XY 0x0054
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#define ATR_W 0x0058
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#define ATR_H 0x005a
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#define ATR_WH 0x0058
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#define ATR_OFFSET 0x005c
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#define ATR_SRC_OFFSET 0x005e
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#define ATR_FG 0x0060
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#define ATR_BG 0x0064
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/* DEC layout */
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#define DEC_COMMAND_MASK 0x0000003f
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#define DEC_COMMAND_SHIFT 0
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#define DEC_DIR_X_REVERSE 0x00000040
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#define DEC_DIR_Y_REVERSE 0x00000080
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#define DEC_DIR_Y_MAJOR 0x00000100
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#define DEC_SRC_LINEAR 0x00000200
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#define DEC_SRC_CONTIGUOUS 0x00000800
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#define DEC_MONOCHROME 0x00001000
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#define DEC_SRC_TRANSPARENT 0x00002000
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#define DEC_DEPTH_MASK 0x0001c000
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#define DEC_DEPTH_SHIFT 14
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#define DEC_DST_LINEAR 0x00040000
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#define DEC_DST_CONTIGUOUS 0x00080000
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#define DEC_DST_TRANSPARENT 0x00100000
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#define DEC_DST_TRANSPARENT_POLARITY 0x00200000
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#define DEC_PATTERN_MASK 0x00c00000
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#define DEC_PATTERN_SHIFT 22
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#define DEC_WIDTH_MASK 0x07000000
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#define DEC_WIDTH_SHIFT 24
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#define DEC_UPDATE_MASK 0x18000000
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#define DEC_UPDATE_SHIFT 27
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#define DEC_START_MASK 0x60000000
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#define DEC_START_SHIFT 29
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#define DEC_START 0x80000000
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/* DEC commands */
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#define DEC_COMMAND_NOP 0x00
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#define DEC_COMMAND_BLT 0x01 /* screen to screen blt */
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#define DEC_COMMAND_RECT 0x02 /* rectangle fill */
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#define DEC_COMMAND_BLT_STRETCH 0x03 /* blt and stretch */
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#define DEC_COMMAND_STRIP 0x04 /* strip pattern */
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#define DEC_COMMAND_HOST_BLT 0x08 /* host to screen blt */
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#define DEC_COMMAND_SCREEN_BLT 0x09 /* screen to host blt */
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#define DEC_COMMAND_VECT_ENDP 0x0c /* vector with end point */
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#define DEC_COMMAND_VECT_NO_ENDP 0x0d /* vector without end point */
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/* depth */
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#define DEC_DEPTH_8 0x01
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#define DEC_DEPTH_16 0x02
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#define DEC_DEPTH_32 0x03
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#define DEC_DEPTH_24 0x04
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/* width */
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#define DEC_WIDTH_LINEAR 0x00
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#define DEC_WIDTH_640 0x01
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#define DEC_WIDTH_800 0x02
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#define DEC_WIDTH_1024 0x04
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#define DEC_WIDTH_1152 0x05
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#define DEC_WIDTH_1280 0x06
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#define DEC_WIDTH_1600 0x07
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/* update mode */
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#define DEC_UPDATE_NONE 0x00
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#define DEC_UPDATE_TOP_RIGHT 0x01
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#define DEC_UPDATE_BOTTOM_LEFT 0x02
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#define DEC_UPDATE_LASTPIX 0x03
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/* quickstart mode - operation starts as soon as given register is written to */
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#define DEC_START_DIMX 0x01
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#define DEC_START_SRC 0x02
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#define DEC_START_DST 0x03
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/* ROP */
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#define ROP_DST 0x66
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#define ROP_SRC 0xcc
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#define ROP_INV 0x33
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#define ROP_PATTERN 0xf0
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/*
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* Configuration Registers
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*/
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#define ATR_PIXEL 0x0080 /* byte access */
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#define PIXEL_DEPTH_MASK 0x0f
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#define PIXEL_DEPTH_SHIFT 0
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/* pixel depth */
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#define PIXEL_4 0x01
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#define PIXEL_8 0x02
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#define PIXEL_15 0x0c
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#define PIXEL_16 0x0d
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#define PIXEL_24 0x0e
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#define PIXEL_32 0x0f
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#define ATR_APERTURE 0x00c0 /* short access */
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/*
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* DPMS Control
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*/
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#define ATR_DPMS 0x00d0 /* byte access */
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#define DPMS_HSYNC_DISABLE 0x01
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#define DPMS_VSYNC_DISABLE 0x02
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#define DPMS_SYNC_DISABLE_ALL 0x03
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/*
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* RAMDAC
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*/
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#define ATR_COLOR_CORRECTION 0x00e0
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#define ATR_MCLK 0x00e8
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#define ATR_PCLK 0x00ec
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/*
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* Hardware Cursor
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*
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* The position can not become negative; the offset register, encoded as
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* (signed y delta << 8) | signed x delta, allow the cursor image to
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* cross the upper-left corner.
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*/
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#define ATR_CURSOR_ENABLE 0x0140
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#define ATR_CURSOR_FG 0x0141 /* 3:3:2 */
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#define ATR_CURSOR_BG 0x0142 /* 3:3:2 */
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#define ATR_CURSOR_ADDRESS 0x0144 /* in KB from vram */
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#define ATR_CURSOR_POSITION 0x0148
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#define ATR_CURSOR_HOTSPOT 0x014c /* short access */
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/*
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* Identification Register
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*/
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#define ATR_ID 0x0182
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#define ID_AP6422 0x6422
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#define ID_AT24 0x6424
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#define ID_AT3D 0x643d
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/*
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* Status Registers
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*/
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#define ATR_FIFO_STATUS 0x01fc
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#define ATR_BLT_STATUS 0x01fd
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#define FIFO_MASK 0x0f
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#define FIFO_SHIFT 0
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#define FIFO_AP6422 4
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#define FIFO_AT24 8
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#define BLT_HOST_BUSY 0x01
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#define BLT_ENGINE_BUSY 0x04
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#define MGX_REG_ATREG_OFFSET 0x000b0000
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#endif /* MGX_REG_H */
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