128 lines
5.8 KiB
C
128 lines
5.8 KiB
C
/* $NetBSD: dbrireg.h,v 1.6 2008/05/09 03:12:49 macallan Exp $ */
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/*
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* Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
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* Copyright (c) 1998, 1999 Brent Baccala (baccala@freesoft.org)
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* Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill@netbsd.org>
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* Copyright (c) 2005 Michael Lorenz <macallan@netbsd.org>
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* All rights reserved.
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*
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* This driver is losely based on a Linux driver written by Rudolf Koenig and
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* Brent Baccala who kindly gave their permission to use their code in a
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* BSD-licensed driver.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef DBRI_REG_H
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#define DBRI_REG_H
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#define DBRI_REG0 0x00L /* status and control */
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#define DBRI_COMMAND_VALID (1<<15)
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#define DBRI_BURST_4 (1<<14) /* allow 4-word sbus bursts */
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#define DBRI_BURST_16 (1<<13) /* allow 16-word sbus bursts */
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#define DBRI_BURST_8 (1<<12) /* allow 8-word sbus bursts */
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#define DBRI_CHI_ACTIVATE (1<<4) /* allow activation of CHI interface */
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#define DBRI_DISABLE_MASTER (1<<2) /* disable master mode */
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#define DBRI_SOFT_RESET (1<<0) /* soft reset */
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#define DBRI_REG1 0x04UL /* mode and interrupt */
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#define DBRI_MRR (1<<4) /* multiple error ack on sbus */
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#define DBRI_MLE (1<<3) /* multiple late error on sbus */
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#define DBRI_LBG (1<<2) /* lost bus grant on sbus */
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#define DBRI_MBE (1<<1) /* burst error on sbus */
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#define DBRI_REG2 0x08UL /* parallel I/O */
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#define DBRI_PIO2_ENABLE (1<<6) /* enable pin 2 */
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#define DBRI_PIO_ENABLE_ALL (0xf0) /* enable all the pins */
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#define DBRI_PIO3 (1<<3) /* pin 3: 1: data mode, 0: ctrl mode */
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#define DBRI_PIO2 (1<<2) /* pin 2: 1: onboard PDN */ /* XXX according to SPARCbook manual this is RESET */
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#define DBRI_PIO1 (1<<1) /* pin 1: 0: reset */ /* XXX according to SPARCbook manual this is PDN */
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#define DBRI_PIO0 (1<<0) /* pin 0: 1: speakerbox PDN */
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#define DBRI_REG8 0x20UL /* command queue pointer */
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#define DBRI_COMMAND_WAIT 0x0
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#define DBRI_COMMAND_PAUSE 0x1
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#define DBRI_COMMAND_IIQ 0x3
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#define DBRI_COMMAND_SDP 0x5
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#define DBRI_COMMAND_CDP 0x6
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#define DBRI_COMMAND_DTS 0x7
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#define DBRI_COMMAND_SSP 0x8
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#define DBRI_COMMAND_CHI 0x9
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#define DBRI_COMMAND_CDM 0xe /* CHI data mode */
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/* interrupts */
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#define DBRI_INTR_BRDY 1 /* buffer ready for processing */
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#define DBRI_INTR_CMDI 6 /* command has been read */
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#define DBRI_INTR_XCMP 8 /* transmission of frame complete */
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#define DBRI_INTR_SBRI 9 /* BRI status change info */
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#define DBRI_INTR_FXDT 10 /* fixed data change */
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#define DBRI_INTR_UNDR 15 /* DMA underrun */
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#define DBRI_INTR_CMD 38
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/* setup data pipe */
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/* IRM */
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#define DBRI_SDP_2SAME (1<<18) /* report 2nd time in a row recv val */
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#define DBRI_SDP_CHANGE (2<<18) /* report any changes */
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#define DBRI_SDP_EVERY (3<<18) /* report any changes */
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/* pipe data mode */
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#define DBRI_SDP_FIXED (6<<13) /* short only */
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#define DBRI_SDP_TO_SER (1<<12) /* direction */
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#define DBRI_SDP_FROM_SER (0<<12) /* direction */
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#define DBRI_SDP_CLEAR (1<<7) /* clear */
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#define DBRI_SDP_VALID_POINTER (1<<10) /* pointer valid */
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#define DBRI_SDP_MEM (0<<13) /* to/from memory */
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#define DBRI_SDP_MSB (1<<11) /* bit order */
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#define DBRI_SDP_LSB (0<<11) /* bit order */
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/* define time slot */
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#define DBRI_DTS_VI (1<<17) /* valid input time-slot descriptor */
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#define DBRI_DTS_VO (1<<16) /* valid output time-slot descriptor */
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#define DBRI_DTS_INS (1<<15) /* insert time-slot */
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#define DBRI_DTS_DEL (0<<15) /* delete time-slot */
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#define DBRI_DTS_PRVIN(v) ((v)<<10) /* previous in-pipe */
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#define DBRI_DTS_PRVOUT(v) ((v)<<5) /* previous out-pipe */
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/* time slot defines */
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#define DBRI_TS_ANCHOR (7<<10) /* starting short pipes */
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#define DBRI_TS_NEXT(v) ((v)<<0) /* pipe #: 0-15 long, 16-21 short */
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#define DBRI_TS_LEN(v) ((v)<<24) /* # of bits in this timeslot */
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#define DBRI_TS_CYCLE(v) ((v)<<14) /* bit count at start of cycle */
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/* concentration highway interface (CHI) modes */
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#define DBRI_CHI_CHICM(v) ((v)<<16) /* clock mode */
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#define DBRI_CHI_BPF(v) ((v)<<0) /* bits per frame */
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#define DBRI_CHI_FD (1<<11) /* frame drive */
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/* CHI data mode */
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#define DBRI_CDM_XCE (1<<2) /* transmit on rising edge of CHICK */
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#define DBRI_CDM_XEN (1<<1) /* transmit highway enable */
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#define DBRI_CDM_REN (1<<0) /* receive highway enable */
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/* transmit descriptor defines */
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#define DBRI_TD_CNT(v) ((v)<<16) /* # valid bytes in buffer */
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#define DBRI_TD_STATUS(v) ((v)&0xff) /* transmit status */
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#define DBRI_TD_EOF (1<<31) /* end of frame */
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#define DBRI_TD_FINAL (1<<15) /* final interrupt */
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#define DBRI_TD_IDLE (1<<13) /* transmit idle characters */
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#define DBRI_TD_TBC (1<<0) /* transmit buffer complete */
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#endif /* DBRI_REG_H */
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