117 lines
4.1 KiB
C
117 lines
4.1 KiB
C
/* $NetBSD: pl181reg.h,v 1.1 2015/01/27 16:33:26 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _PL181REG_H
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#define _PL181REG_H
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#define MMCI_POWER_REG 0x000
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#define MMCI_CLOCK_REG 0x004
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#define MMCI_ARGUMENT_REG 0x008
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#define MMCI_COMMAND_REG 0x00c
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#define MMCI_RESP_CMD_REG 0x010
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#define MMCI_RESP0_REG 0x014
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#define MMCI_RESP1_REG 0x018
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#define MMCI_RESP2_REG 0x01c
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#define MMCI_RESP3_REG 0x020
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#define MMCI_DATA_TIMER_REG 0x024
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#define MMCI_DATA_LENGTH_REG 0x028
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#define MMCI_DATA_CTRL_REG 0x02c
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#define MMCI_DATA_CNT_REG 0x030
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#define MMCI_STATUS_REG 0x034
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#define MMCI_CLEAR_REG 0x038
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#define MMCI_MASK0_REG 0x03c
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#define MMCI_MASK1_REG 0x040
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#define MMCI_FIFO_CNT_REG 0x048
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#define MMCI_FIFO_REG 0x080
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#define MMCI_PERIPH_ID0_REG 0xfe0
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#define MMCI_PERIPH_ID1_REG 0xfe4
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#define MMCI_PERIPH_ID2_REG 0xfe8
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#define MMCI_PERIPH_ID3_REG 0xfec
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#define MMCI_PCELL_ID0_REG 0xff0
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#define MMCI_PCELL_ID1_REG 0xff4
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#define MMCI_PCELL_ID2_REG 0xff8
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#define MMCI_PCELL_ID3_REG 0xffc
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#define MMCI_POWER_CTRL __BITS(1,0)
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#define MMCI_POWER_CTRL_OFF 0
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#define MMCI_POWER_CTRL_POWERUP 2
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#define MMCI_POWER_CTRL_POWERON 3
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#define MMCI_POWER_VOLTAGE __BITS(5,2)
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#define MMCI_POWER_OD __BIT(6)
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#define MMCI_POWER_ROD __BIT(7)
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#define MMCI_CLOCK_CLKDIV __BITS(7,0)
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#define MMCI_CLOCK_ENABLE __BIT(8)
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#define MMCI_CLOCK_PWRSAVE __BIT(9)
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#define MMCI_CLOCK_BYPASS __BIT(10)
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#define MMCI_COMMAND_CMDINDEX __BITS(5,0)
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#define MMCI_COMMAND_RESPONSE __BIT(6)
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#define MMCI_COMMAND_LONGRSP __BIT(7)
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#define MMCI_COMMAND_INTERRUPT __BIT(8)
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#define MMCI_COMMAND_PENDING __BIT(9)
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#define MMCI_COMMAND_ENABLE __BIT(10)
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#define MMCI_RESP_CMD __BITS(5,0)
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#define MMCI_DATA_LENGTH __BITS(15,0)
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#define MMCI_DATA_CTRL_ENABLE __BIT(0)
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#define MMCI_DATA_CTRL_DIRECTION __BIT(1)
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#define MMCI_DATA_CTRL_MODE __BIT(2)
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#define MMCI_DATA_CTRL_DMAENABLE __BIT(3)
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#define MMCI_DATA_CTRL_BLOCKSIZE __BITS(7,4)
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#define MMCI_DATA_CNT __BITS(15,0)
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#define MMCI_INT_CMD_CRC_FAIL __BIT(0)
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#define MMCI_INT_DATA_CRC_FAIL __BIT(1)
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#define MMCI_INT_CMD_TIMEOUT __BIT(2)
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#define MMCI_INT_DATA_TIMEOUT __BIT(3)
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#define MMCI_INT_TX_UNDERRUN __BIT(4)
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#define MMCI_INT_RX_OVERRUN __BIT(5)
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#define MMCI_INT_CMD_RESP_END __BIT(6)
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#define MMCI_INT_CMD_SENT __BIT(7)
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#define MMCI_INT_DATA_END __BIT(8)
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#define MMCI_INT_DATA_BLOCK_END __BIT(10)
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#define MMCI_INT_CMD_ACTIVE __BIT(11)
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#define MMCI_INT_TX_ACTIVE __BIT(12)
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#define MMCI_INT_RX_ACTIVE __BIT(13)
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#define MMCI_INT_TX_FIFO_HALF_EMPTY __BIT(14)
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#define MMCI_INT_RX_FIFO_HALF_FULL __BIT(15)
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#define MMCI_INT_TX_FIFO_FULL __BIT(16)
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#define MMCI_INT_RX_FIFO_FULL __BIT(17)
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#define MMCI_INT_TX_FIFO_EMPTY __BIT(18)
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#define MMCI_INT_RX_FIFO_EMPTY __BIT(19)
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#define MMCI_INT_TX_DATA_AVAIL __BIT(20)
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#define MMCI_INT_RX_DATA_AVAIL __BIT(21)
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#define MMCI_FIFO_CNT __BITS(14,0)
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#endif /* !_PL181REG_H */
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