297 lines
13 KiB
C
297 lines
13 KiB
C
/* $NetBSD: cd18xxreg.h,v 1.4 2008/05/29 14:51:27 mrg Exp $ */
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/*
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* Copyright (c) 1998, 2001 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* cirrus-logic CL-CD180/CD1864/CD1865 register definitions, from the
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* CL-CD1865 data book.
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*/
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/*
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* available registers for us.
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*
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* the cd1865 provides 4 types of registers: global, indexed indirect,
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* channel, and unavailable. we should never touch the unavailable, as it
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* may cause the cd1865 to fail. the indexed indirect registers are
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* really pointers to the correct channel we are currently servicing, and
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* as such must only be accessed during service-request service routines.
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* global registers set and provide common functionality between all of
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* the channels. channel registers only affect the specific channel.
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* access to channel registers is limited to the current channel, as
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* specified in the CAR register, ie. to access different channels, the CAR
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* register must be changed first.
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*/
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/*
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* the registers themselves.
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*/
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/* global registers */
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#define CD18xx_GFRCR 0x6b /* global firmware revision code */
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#define CD18xx_SRCR 0x66 /* service request configuration */
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#define CD18xx_PPRH 0x70 /* prescaler period (high) */
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#define CD18xx_PPRL 0x71 /* prescaler period (low) */
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#define CD18xx_MSMR 0x61 /* modem service match */
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#define CD18xx_TSMR 0x62 /* transmit service match */
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#define CD18xx_RSMR 0x63 /* receive service match */
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#define CD18xx_GSVR 0x40 /* global service vector */
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#define CD18xx_SRSR 0x65 /* service request status */
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#define CD18xx_MRAR 0x75 /* modem request acknowledge */
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#define CD18xx_TRAR 0x76 /* transmit request acknowledge */
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#define CD18xx_RRAR 0x77 /* receive request acknowledge */
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#define CD18xx_GSCR1 0x41 /* global service channel (1) */
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#define CD18xx_GSCR2 0x42 /* global service channel (2) */
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#define CD18xx_GSCR3 0x43 /* global service channel (3) */
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#define CD18xx_CAR 0x64 /* channel access register */
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/* indexed indirect registers */
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#define CD18xx_RDCR 0x07 /* receive data count */
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#define CD18xx_RDR 0x78 /* receiver data register */
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#define CD18xx_RCSR 0x7a /* receiver channel status */
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#define CD18xx_TDR 0x7b /* transmit data register */
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#define CD18xx_EOSRR 0x7f /* end of service request */
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/* channel registers */
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#define CD18xx_SRER 0x02 /* service request enable */
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#define CD18xx_CCR 0x01 /* channel command */
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#define CD18xx_COR1 0x03 /* channel option (1) */
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#define CD18xx_COR2 0x04 /* channel option (2) */
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#define CD18xx_COR3 0x05 /* channel option (3) */
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#define CD18xx_CCSR 0x06 /* channel control status */
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#define CD18xx_RBR 0x33 /* receiver bit */
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#define CD18xx_RTPR 0x18 /* receive time-out period */
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#define CD18xx_RBPRH 0x31 /* receive bit rate period (high) */
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#define CD18xx_RBPRL 0x32 /* receive bit rate period (low) */
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#define CD18xx_TBPRH 0x39 /* transmit bit rate period (high) */
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#define CD18xx_TBPRL 0x3a /* transmit bit rate period (low) */
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#define CD18xx_SCHR1 0x09 /* special character (1) */
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#define CD18xx_SCHR2 0x0a /* special character (2) */
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#define CD18xx_SCHR3 0x0b /* special character (3) */
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#define CD18xx_SCHR4 0x0c /* special character (4) */
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#define CD18xx_MCR 0x10 /* modem change */
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#define CD18xx_MCOR1 0x10 /* modem change option (1) */
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#define CD18xx_MCOR2 0x11 /* modem change option (2) */
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#define CD18xx_MSVR 0x28 /* modem signal value */
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#define CD18xx_MSVRTS 0x29 /* modem signal value RTS */
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#define CD18xx_MSVDTR 0x2a /* mdoem signal value DTR */
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/*
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* inside the registers
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*/
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/* global registers */
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/* global firmware revision code */
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#define CD180_GFRCR_REV_B 0x81 /* CL-CD180B */
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#define CD180_GFRCR_REV_C 0x82 /* CL-CD180C */
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#define CD1864_GFRCR_REVISION_A 0x82 /* CL-CD1864A */
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#define CD1865_GFRCR_REVISION_A 0x83 /* CL-CD1865A */
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#define CD1865_GFRCR_REVISION_B 0x84 /* CL-CD1865B */
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#define CD1865_GFRCR_REVISION_C 0x85 /* CL-CD1865C */
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/* service request configuration register */
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#define CD18xx_SRCR_PKGTYP 0x80 /* package type (RO) */
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#define CD18xx_SRCR_REGACKEN 0x40 /* enable register acks */
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#define CD18xx_SRCR_DAISYEN 0x20 /* enable daisy-chain */
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#define CD18xx_SRCR_GLOBPRI 0x10 /* global priority */
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#define CD18xx_SRCR_UNFAIR 0x08 /* unfair override */
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#define CD18xx_SRCR_AUTOPRI 0x02 /* auto prioritizing */
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#define CD18xx_SRCR_PRISEL 0x01 /* priority selection */
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/* global service vector register */
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#define CD18xx_GSVR_CLEAR 0x00 /* clear GSVR for reset */
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#define CD18xx_GSVR_READY 0xff /* modem is ready */
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#define CD18xx_GSVR_IDMASK 0xf8 /* unique ID per-chip */
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#define CD18xx_GSVR_SETID(sc) ((((sc)->sc_chip_id & ~1) << 5) | \
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(((sc)->sc_chip_id & 1) << 3))
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#define CD18xx_GSVR_GROUPTYPE 0x07 /* group/type */
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#define CD18xx_GSVR_NOREQPEND 0x00 /* no request pending */
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#define CD18xx_GSVR_MODEM 0x01 /* modem signal change */
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#define CD18xx_GSVR_TXDATA 0x02 /* tx data */
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#define CD18xx_GSVR_RXDATA 0x03 /* rx good data */
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#define CD18xx_GSVR_RXEXCEPTION 0x07 /* request exception */
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#define CD18xx_GSVR_RXINTR(x) \
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(((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_RXDATA || \
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((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_RXEXCEPTION)
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#define CD18xx_GSVR_TXINTR(x) \
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(((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_TXDATA)
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#define CD18xx_GSVR_MXINTR(x) \
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(((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_MODEM)
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/* service request status register */
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#define CD18xx_SRSR_CONTEXT 0xc0 /* service request context */
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#define CD18xx_SRSR_PENDING 0x15 /* get status bits for each */
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#define CD18xx_SRSR_RxPEND 0x10 /* got a Rx interrupt */
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#define CD18xx_SRSR_TxPEND 0x04 /* got a Tx interrupt */
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#define CD18xx_SRSR_MxPEND 0x01 /* got a modem interrupt */
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/* global service channel registers */
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#define CD18xx_GSCR_USER1 0xe0 /* 3 bits of user-defined data */
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#define CD18xx_GSCR_CAR 0x1c /* CAR of current channel */
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#define CD18xx_GSCR_USER2 0x03 /* 2 bits of user-defined data */
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/* indexed indirect registers */
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/* receive data count register */
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#define CD18xx_RDCR_ZERO 0xf0 /* reserved, must be zero */
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#define CD18xx_RDCR_GOODBYTES 0x0f /* number of good bytes */
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/* receive character status register */
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#define CD18xx_RCSR_TIMEOUT 0x80 /* timeout has occurred on channel */
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#define CD18xx_RCSR_SCD 0x70 /* special character detect */
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#define CD18xx_RCSR_BREAK 0x08 /* line break detected */
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#define CD18xx_RCSR_PARITYERR 0x04 /* parity error detected */
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#define CD18xx_RCSR_FRAMERR 0x02 /* framing error detected */
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#define CD18xx_RCSR_OVERRUNERR 0x01 /* overrun error detected */
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/* transmit data register */
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#define CD18xx_TDR_ETC_BYTE 0x00 /* first byte of break message */
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#define CD18xx_TDR_BREAK_BYTE 0x81 /* first byte of break message */
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#define CD18xx_TDR_NOBREAK_BYTE 0x83 /* first byte of clean break message */
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/* channel registers */
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/* service request enable register */
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#define CD18xx_SRER_DSR 0x80 /* DSR service request */
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#define CD18xx_SRER_CD 0x40 /* CD service request */
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#define CD18xx_SRER_CTS 0x20 /* CTS service request */
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#define CD18xx_SRER_Rx 0x10 /* Rx data service request */
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#define CD18xx_SRER_RxSC 0x08 /* Rx special char service request */
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#define CD18xx_SRER_Tx 0x04 /* Tx ready service request */
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#define CD18xx_SRER_TxEMPTY 0x02 /* Tx empty service request */
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#define CD18xx_SRER_NNDT 0x01 /* no new data timeout service request */
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/* channel command register */
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#define CD18xx_CCR_RESET 0x80 /* reset channel command */
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#define CD18xx_CCR_CORCHG 0x40 /* COR change command */
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#define CD18xx_CCR_SENDSC 0x20 /* send special character command */
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#define CD18xx_CCR_CHANCTL 0x10 /* channel control command */
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/* bits inside CCR's least significant half-byte */
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#define CD18xx_CCR_RESET_HARD 0x01 /* full, hard reset */
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#define CD18xx_CCR_RESET_CHAN 0x00 /* reset only the current channel */
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#define CD18xx_CCR_CORCHG_COR3 0x08 /* change COR3 command */
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#define CD18xx_CCR_CORCHG_COR2 0x04 /* change COR2 command */
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#define CD18xx_CCR_CORCHG_COR1 0x02 /* change COR1 command */
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#define CD18xx_CCR_SENDSC_SEND1 0x01 /* send SC 1, or 1&3 */
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#define CD18xx_CCR_SENDSC_SEND2 0x02 /* send SC 2, or 2&4 */
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#define CD18xx_CCR_SENDSC_SEND3 0x03 /* send SC 3 */
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#define CD18xx_CCR_SENDSC_SEND4 0x04 /* send SC 4 */
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/* note that these are slower than enabling/disabling SRER */
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#define CD18xx_CCR_CHANCTL_TxEN 0x08 /* transmitter enable */
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#define CD18xx_CCR_CHANCTL_TxDI 0x04 /* transmitter disable */
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#define CD18xx_CCR_CHANCTL_RxEN 0x02 /* receiver enable */
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#define CD18xx_CCR_CHANCTL_RxDI 0x01 /* receiver disable */
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/* channel option register 1 */
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#define CD18xx_COR1_PARITY 0x80 /* parity */
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#define CD18xx_COR1_PARITY_ODD 0x80 /* odd parity */
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#define CD18xx_COR1_PARITY_EVEN 0x00 /* even parity */
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#define CD18xx_COR1_PARITY_MODE 0x60 /* parity mode */
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#define CD18xx_COR1_PARITY_NONE 0x00 /* no parity */
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#define CD18xx_COR1_PARITY_FORCE 0x20 /* force parity */
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#define CD18xx_COR1_PARITY_NORMAL 0x40 /* normal parity */
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#define CD18xx_COR1_IGNORE 0x10 /* parity ignore mode */
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#define CD18xx_COR1_STOPBITLEN 0x0c /* stop bit length */
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#define CD18xx_COR1_STOPBIT_1 0x00 /* 1 stop bit */
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#define CD18xx_COR1_STOPBIT_1_5 0x04 /* 1.5 stop bits */
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#define CD18xx_COR1_STOPBIT_2 0x08 /* 2 stop bits */
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#define CD18xx_COR1_STOPBIT_2_5 0x0c /* 2.5 stop bits */
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#define CD18xx_COR1_CHARLEN 0x03 /* character length */
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#define CD18xx_COR1_CS5 0x00 /* 5 bit chars */
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#define CD18xx_COR1_CS6 0x01 /* 7 bit chars */
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#define CD18xx_COR1_CS7 0x02 /* 7 bit chars */
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#define CD18xx_COR1_CS8 0x03 /* 8 bit chars */
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/* channel option register 2 */
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#define CD18xx_COR2_IXM 0x80 /* implied XON mode */
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#define CD18xx_COR2_TxIBE 0x40 /* Tx inband flow control auto enable */
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#define CD18xx_COR2_ETC 0x20 /* embedded Tx command enable */
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#define CD18xx_COR2_LLM 0x10 /* local loopback mode */
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#define CD18xx_COR2_RLM 0x08 /* remote loopback mode */
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#define CD18xx_COR2_RTSAOE 0x04 /* RTS auto output enable */
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#define CD18xx_COR2_CTSAE 0x02 /* CTS auto enable */
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#define CD18xx_COR2_DSRAE 0x01 /* DSR auto enable */
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/* channel option register 3 */
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#define CD18xx_COR3_XONCH 0x80 /* XON character definition */
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#define CD18xx_COR3_XOFFCH 0x40 /* XOFF character definition */
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#define CD18xx_COR3_FCTM 0x20 /* flow control transparency mode */
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#define CD18xx_COR3_SCDE 0x10 /* special character detection enable */
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#define CD18xx_COR3_FIFOTHRESH 0x08 /* Rx FIFO threshold */
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/* channel control status register */
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#define CD18xx_CCSR_RxEN 0x80 /* Rx enable */
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#define CD18xx_CCSR_RxFLOFF 0x40 /* Rx flow control off enable */
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#define CD18xx_CCSR_RxFLON 0x20 /* Rx flow control on enable */
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#define CD18xx_CCSR_TxEN 0x08 /* Tx enable */
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#define CD18xx_CCSR_TxFLOFF 0x04 /* Tx flow control off enable */
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#define CD18xx_CCSR_TxFLON 0x02 /* Tx flow control on enable */
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/* receiver bit register */
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#define CD18xx_RBR_RxD 0x40 /* last RxD input */
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#define CD18xx_RBR_STARTHUNT 0x20 /* hunting for a start bit */
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/* bit rate period resisters */
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#define CD18xx_xBRPR_TPC 0x10 /* ticks per character */
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/* mode change register */
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#define CD18xx_MCR_DSR 0x80 /* DSR changed */
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#define CD18xx_MCR_CD 0x40 /* CD changed */
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#define CD18xx_MCR_CTS 0x20 /* CST changed */
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/* modem change option register 1 */
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#define CD18xx_MCOR1_DSR 0x80 /* high-to-low on DSR */
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#define CD18xx_MCOR1_CD 0x40 /* high-to-low on CD */
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#define CD18xx_MCOR1_CTS 0x20 /* high-to-low on CTS */
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#define CD18xx_MCOR1_DTR 0x08 /* high-to-low on DSR mode */
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/* modem change option register 2 */
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#define CD18xx_MCOR2_DSR 0x80 /* low-to-high on DSR */
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#define CD18xx_MCOR2_CD 0x40 /* low-to-high on CD */
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#define CD18xx_MCOR2_CTS 0x20 /* low-to-high on CST */
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/* modem signal value register */
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#define CD18xx_MSVR_DSR 0x80 /* current DSR state */
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#define CD18xx_MSVR_CD 0x40 /* current CD state */
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#define CD18xx_MSVR_CTS 0x20 /* current CTS state */
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#define CD18xx_MSVR_DTR 0x02 /* current DTR state */
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#define CD18xx_MSVR_RTS 0x01 /* current RTS state */
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#define CD18xx_MSVR_RESET (CD18xx_MSVR_DSR|CD18xx_MSVR_CD| \
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CD18xx_MSVR_CTS|CD18xx_MSVR_DTR| \
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CD18xx_MSVR_RTS)
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/* modem signal value request-to-send register */
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#define CD18xx_MSVRTS_RTS 0x01 /* change RTS and not DTR */
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/* modem signal value data-terminal-ready register */
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#define CD18xx_MSVDTR_DTR 0x01 /* change DTR and not RTS */
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