1080 lines
30 KiB
C
1080 lines
30 KiB
C
/* $NetBSD: anx_dp.c,v 1.2 2020/01/04 12:08:32 jmcneill Exp $ */
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/*-
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* Copyright (c) 2019 Jonathan A. Kollasch <jakllsch@kollasch.net>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: anx_dp.c,v 1.2 2020/01/04 12:08:32 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/conf.h>
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#include <dev/ic/anx_dp.h>
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#if ANXDP_AUDIO
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#include <dev/audio/audio_dai.h>
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#endif
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_edid.h>
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#define ANXDP_DP_TX_VERSION 0x010
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#define ANXDP_TX_SW_RESET 0x014
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#define RESET_DP_TX __BIT(0)
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#define ANXDP_FUNC_EN_1 0x018
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#define MASTER_VID_FUNC_EN_N __BIT(7)
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#define RK_VID_CAP_FUNC_EN_N __BIT(6)
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#define SLAVE_VID_FUNC_EN_N __BIT(5)
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#define RK_VID_FIFO_FUNC_EN_N __BIT(5)
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#define AUD_FIFO_FUNC_EN_N __BIT(4)
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#define AUD_FUNC_EN_N __BIT(3)
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#define HDCP_FUNC_EN_N __BIT(2)
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#define CRC_FUNC_EN_N __BIT(1)
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#define SW_FUNC_EN_N __BIT(0)
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#define ANXDP_FUNC_EN_2 0x01c
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#define SSC_FUNC_EN_N __BIT(7)
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#define AUX_FUNC_EN_N __BIT(2)
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#define SERDES_FIFO_FUNC_EN_N __BIT(1)
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#define LS_CLK_DOMAIN_FUNC_EN_N __BIT(0)
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#define ANXDP_VIDEO_CTL_1 0x020
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#define VIDEO_EN __BIT(7)
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#define VIDEO_MUTE __BIT(6)
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#define ANXDP_VIDEO_CTL_2 0x024
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#define ANXDP_VIDEO_CTL_3 0x028
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#define ANXDP_VIDEO_CTL_4 0x02c
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#define ANXDP_VIDEO_CTL_8 0x03c
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#define ANXDP_VIDEO_CTL_10 0x044
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#define F_SEL __BIT(4)
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#define SLAVE_I_SCAN_CFG __BIT(2)
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#define SLAVE_VSYNC_P_CFG __BIT(1)
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#define SLAVE_HSYNC_P_CFG __BIT(0)
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#define ANXDP_PLL_REG_1 0x0fc
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#define REF_CLK_24M __BIT(0)
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#define RKANXDP_PD 0x12c
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#define DP_INC_BG __BIT(7)
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#define DP_EXP_PD __BIT(6)
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#define DP_PHY_PD __BIT(5)
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#define RK_AUX_PD __BIT(5)
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#define AUX_PD __BIT(4)
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#define RK_PLL_PD __BIT(4)
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#define CHx_PD(x) __BIT(x) /* 0<=x<=3 */
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#define DP_ALL_PD __BITS(7,0)
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#define ANXDP_LANE_MAP 0x35c
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#define ANXDP_ANALOG_CTL_1 0x370
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#define TX_TERMINAL_CTRL_50_OHM __BIT(4)
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#define ANXDP_ANALOG_CTL_2 0x374
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#define SEL_24M __BIT(3)
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#define TX_DVDD_BIT_1_0625V 0x4
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#define ANXDP_ANALOG_CTL_3 0x378
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#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
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#define VCO_BIT_600_MICRO (0x5 << 0)
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#define ANXDP_PLL_FILTER_CTL_1 0x37c
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#define PD_RING_OSC __BIT(6)
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#define AUX_TERMINAL_CTRL_50_OHM (2 << 4)
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#define TX_CUR1_2X __BIT(2)
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#define TX_CUR_16_MA 3
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#define ANXDP_TX_AMP_TUNING_CTL 0x380
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#define ANXDP_AUX_HW_RETRY_CTL 0x390
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#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) __SHIFTIN((x), __BITS(10,8))
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#define AUX_HW_RETRY_INTERVAL_600_US __SHIFTIN(0, __BITS(4,3))
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#define AUX_HW_RETRY_INTERVAL_800_US __SHIFTIN(1, __BITS(4,3))
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#define AUX_HW_RETRY_INTERVAL_1000_US __SHIFTIN(2, __BITS(4,3))
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#define AUX_HW_RETRY_INTERVAL_1800_US __SHIFTIN(3, __BITS(4,3))
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#define AUX_HW_RETRY_COUNT_SEL(x) __SHIFTIN((x), __BITS(2,0))
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#define ANXDP_COMMON_INT_STA_1 0x3c4
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#define PLL_LOCK_CHG __BIT(6)
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#define ANXDP_COMMON_INT_STA_2 0x3c8
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#define ANXDP_COMMON_INT_STA_3 0x3cc
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#define ANXDP_COMMON_INT_STA_4 0x3d0
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#define ANXDP_DP_INT_STA 0x3dc
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#define INT_HPD __BIT(6)
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#define HW_TRAINING_FINISH __BIT(5)
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#define RPLY_RECEIV __BIT(1)
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#define AUX_ERR __BIT(0)
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#define ANXDP_SYS_CTL_1 0x600
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#define DET_STA __BIT(2)
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#define FORCE_DET __BIT(1)
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#define DET_CTRL __BIT(0)
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#define ANXDP_SYS_CTL_2 0x604
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#define ANXDP_SYS_CTL_3 0x608
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#define HPD_STATUS __BIT(6)
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#define F_HPD __BIT(5)
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#define HPD_CTRL __BIT(4)
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#define HDCP_RDY __BIT(3)
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#define STRM_VALID __BIT(2)
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#define F_VALID __BIT(1)
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#define VALID_CTRL __BIT(0)
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#define ANXDP_SYS_CTL_4 0x60c
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#define ANXDP_PKT_SEND_CTL 0x640
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#define ANXDP_HDCP_CTL 0x648
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#define ANXDP_LINK_BW_SET 0x680
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#define ANXDP_LANE_COUNT_SET 0x684
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#define ANXDP_TRAINING_PTN_SET 0x688
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#define SCRAMBLING_DISABLE __BIT(5)
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#define SW_TRAINING_PATTERN_SET_PTN2 __SHIFTIN(2, __BITS(1,0))
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#define SW_TRAINING_PATTERN_SET_PTN1 __SHIFTIN(1, __BITS(1,0))
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#define ANXDP_LNx_LINK_TRAINING_CTL(x) (0x68c + 4 * (x)) /* 0 <= x <= 3 */
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#define MAX_PRE_REACH __BIT(5)
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#define PRE_EMPHASIS_SET(x) __SHIFTIN((x), __BITS(4,3))
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#define MAX_DRIVE_REACH __BIT(2)
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#define DRIVE_CURRENT_SET(x) __SHIFTIN((x), __BITS(1,0))
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#define ANXDP_DEBUG_CTL 0x6c0
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#define PLL_LOCK __BIT(4)
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#define F_PLL_LOCK __BIT(3)
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#define PLL_LOCK_CTRL __BIT(2)
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#define PN_INV __BIT(0)
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#define ANXDP_LINK_DEBUG_CTL 0x6e0
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#define ANXDP_PLL_CTL 0x71c
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#define ANXDP_PHY_PD 0x720
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#define ANXDP_PHY_TEST 0x724
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#define MACRO_RST __BIT(5)
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#define ANXDP_M_AUD_GEN_FILTER_TH 0x778
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#define ANXDP_AUX_CH_STA 0x780
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#define AUX_BUSY __BIT(4)
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#define AUX_STATUS(x) __SHIFTOUT((x), __BITS(3,0))
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#define ANXDP_AUX_ERR_NUM 0x784
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#define ANXDP_AUX_CH_DEFER_CTL 0x788
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#define DEFER_CTRL_EN __BIT(7)
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#define DEFER_COUNT(x) __SHIFTIN((x), __BITS(6,0))
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#define ANXDP_AUX_RX_COMM 0x78c
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#define AUX_RX_COMM_I2C_DEFER __BIT(3)
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#define AUX_RX_COMM_AUX_DEFER __BIT(1)
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#define ANXDP_BUFFER_DATA_CTL 0x790
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#define BUF_CLR __BIT(7)
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#define BUF_DATA_COUNT(x) __SHIFTIN((x), __BITS(4,0))
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#define ANXDP_AUX_CH_CTL_1 0x794
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#define AUX_LENGTH(x) __SHIFTIN((x) - 1, __BITS(7,4))
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#define AUX_TX_COMM(x) __SHIFTOUT(x, __BITS(3,0))
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#define AUX_TX_COMM_DP __BIT(3)
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#define AUX_TX_COMM_MOT __BIT(2)
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#define AUX_TX_COMM_READ __BIT(0)
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#define ANXDP_AUX_ADDR_7_0 0x798
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#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
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#define ANXDP_AUX_ADDR_15_8 0x79c
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#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
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#define ANXDP_AUX_ADDR_19_16 0x7a0
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#define AUX_ADDR_19_16(x) (((x) >> 16) & 0xf)
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#define ANXDP_AUX_CH_CTL_2 0x7a4
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#define ADDR_ONLY __BIT(1)
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#define AUX_EN __BIT(0)
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#define ANXDP_BUF_DATA(x) (0x7c0 + 4 * (x))
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#define ANXDP_SOC_GENERAL_CTL 0x800
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#define AUDIO_MODE_SPDIF_MODE __BIT(8)
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#define VIDEO_MODE_SLAVE_MODE __BIT(1)
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#define ANXDP_CRC_CON 0x890
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#define ANXDP_PLL_REG_2 0x9e4
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#define ANXDP_PLL_REG_3 0x9e8
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#define ANXDP_PLL_REG_4 0x9ec
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#define ANXDP_PLL_REG_5 0xa00
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#if ANXDP_AUDIO
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enum anxdp_dai_mixer_ctrl {
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ANXDP_DAI_OUTPUT_CLASS,
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ANXDP_DAI_INPUT_CLASS,
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ANXDP_DAI_OUTPUT_MASTER_VOLUME,
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ANXDP_DAI_INPUT_DAC_VOLUME,
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ANXDP_DAI_MIXER_CTRL_LAST
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};
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static void
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anxdp_audio_init(struct anxdp_softc *sc)
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{
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}
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#endif
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static inline const bool
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isrockchip(struct anxdp_softc * const sc)
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{
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return (sc->sc_flags & ANXDP_FLAG_ROCKCHIP) != 0;
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}
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static enum drm_connector_status
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anxdp_connector_detect(struct drm_connector *connector, bool force)
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{
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#if 0
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struct anxdp_connector *anxdp_connector = to_anxdp_connector(connector);
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struct anxdp_softc * const sc = anxdp_connector->sc;
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/* XXX HPD */
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#endif
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return connector_status_connected;
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}
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static void
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anxdp_connector_destroy(struct drm_connector *connector)
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{
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drm_connector_unregister(connector);
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drm_connector_cleanup(connector);
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}
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static const struct drm_connector_funcs anxdp_connector_funcs = {
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.dpms = drm_helper_connector_dpms,
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.detect = anxdp_connector_detect,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = anxdp_connector_destroy,
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};
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static void
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anxdp_analog_power_up_all(struct anxdp_softc * const sc)
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{
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const bus_size_t pd_reg = isrockchip(sc) ? RKANXDP_PD : ANXDP_PHY_PD;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, pd_reg, DP_ALL_PD);
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delay(15);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, pd_reg,
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DP_ALL_PD & ~DP_INC_BG);
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delay(15);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, pd_reg, 0);
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}
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static int
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anxdp_await_pll_lock(struct anxdp_softc * const sc)
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{
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u_int timeout;
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for (timeout = 0; timeout < 100; timeout++) {
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if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_DEBUG_CTL) &
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PLL_LOCK) != 0)
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return 0;
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delay(20);
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}
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return ETIMEDOUT;
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}
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static void
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anxdp_init_hpd(struct anxdp_softc * const sc)
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{
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uint32_t sc3;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_COMMON_INT_STA_4, 0x7);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_DP_INT_STA, INT_HPD);
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sc3 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_3);
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sc3 &= ~(F_HPD | HPD_CTRL);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_3, sc3);
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sc3 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_3);
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sc3 |= F_HPD | HPD_CTRL;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_3, sc3);
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}
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static void
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anxdp_init_aux(struct anxdp_softc * const sc)
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{
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uint32_t fe2, pd, hrc;
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const bus_size_t pd_reg = isrockchip(sc) ? RKANXDP_PD : ANXDP_PHY_PD;
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const uint32_t pd_mask = isrockchip(sc) ? RK_AUX_PD : AUX_PD;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_DP_INT_STA,
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RPLY_RECEIV | AUX_ERR);
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pd = bus_space_read_4(sc->sc_bst, sc->sc_bsh, pd_reg);
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pd |= pd_mask;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, pd_reg, pd);
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delay(11);
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pd = bus_space_read_4(sc->sc_bst, sc->sc_bsh, pd_reg);
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pd &= ~pd_mask;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, pd_reg, pd);
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fe2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_2);
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fe2 |= AUX_FUNC_EN_N;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_2, fe2);
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hrc = AUX_HW_RETRY_COUNT_SEL(0) | AUX_HW_RETRY_INTERVAL_600_US;
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if (!isrockchip(sc))
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hrc |= AUX_BIT_PERIOD_EXPECTED_DELAY(3);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_HW_RETRY_CTL, hrc);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_CH_DEFER_CTL,
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DEFER_CTRL_EN | DEFER_COUNT(1));
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fe2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_2);
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fe2 &= ~AUX_FUNC_EN_N;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_2, fe2);
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}
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static int
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anxdp_connector_get_modes(struct drm_connector *connector)
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{
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struct anxdp_connector *anxdp_connector = to_anxdp_connector(connector);
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struct anxdp_softc * const sc = anxdp_connector->sc;
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struct edid *pedid = NULL;
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int error;
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pedid = drm_get_edid(connector, &sc->sc_dpaux.ddc);
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#if ANXDP_AUDIO
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if (pedid) {
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anxdp_connector->monitor_audio =
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drm_detect_monitor_audio(pedid);
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} else {
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anxdp_connector->monitor_audio = false;
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}
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#endif
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drm_mode_connector_update_edid_property(connector, pedid);
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if (pedid == NULL)
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return 0;
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error = drm_add_edid_modes(connector, pedid);
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drm_edid_to_eld(connector, pedid);
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if (pedid != NULL)
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kfree(pedid);
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return error;
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}
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static struct drm_encoder *
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anxdp_connector_best_encoder(struct drm_connector *connector)
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{
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int enc_id = connector->encoder_ids[0];
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struct drm_mode_object *obj;
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struct drm_encoder *encoder = NULL;
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if (enc_id) {
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obj = drm_mode_object_find(connector->dev, enc_id,
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DRM_MODE_OBJECT_ENCODER);
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if (obj == NULL)
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return NULL;
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encoder = obj_to_encoder(obj);
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}
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return encoder;
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}
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static const struct drm_connector_helper_funcs anxdp_connector_helper_funcs = {
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.get_modes = anxdp_connector_get_modes,
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.best_encoder = anxdp_connector_best_encoder,
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};
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static int
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anxdp_bridge_attach(struct drm_bridge *bridge)
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{
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struct anxdp_softc * const sc = bridge->driver_private;
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struct anxdp_connector *anxdp_connector = &sc->sc_connector;
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struct drm_connector *connector = &anxdp_connector->base;
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int error;
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anxdp_connector->sc = sc;
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connector->polled =
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DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
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connector->interlace_allowed = 0;
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connector->doublescan_allowed = 0;
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drm_connector_init(bridge->dev, connector, &anxdp_connector_funcs,
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connector->connector_type);
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drm_connector_helper_add(connector, &anxdp_connector_helper_funcs);
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error = drm_mode_connector_attach_encoder(connector, bridge->encoder);
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if (error != 0)
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return error;
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return drm_connector_register(connector);
|
|
}
|
|
|
|
static void
|
|
anxdp_macro_reset(struct anxdp_softc * const sc)
|
|
{
|
|
uint32_t val;
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_PHY_TEST);
|
|
val |= MACRO_RST;
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_PHY_TEST, val);
|
|
delay(10);
|
|
val &= ~MACRO_RST;
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_PHY_TEST, val);
|
|
}
|
|
|
|
static void
|
|
anxdp_link_start(struct anxdp_softc * const sc, struct drm_dp_link * const link)
|
|
{
|
|
uint8_t training[4];
|
|
uint32_t val;
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_LINK_BW_SET, drm_dp_link_rate_to_bw_code(link->rate));
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_LANE_COUNT_SET, link->num_lanes);
|
|
if (0 != drm_dp_link_configure(&sc->sc_dpaux, link))
|
|
return;
|
|
|
|
for (u_int i = 0; i < link->num_lanes; i++) {
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
|
|
ANXDP_LNx_LINK_TRAINING_CTL(i));
|
|
val &= ~(PRE_EMPHASIS_SET(3)|DRIVE_CURRENT_SET(3));
|
|
val |= PRE_EMPHASIS_SET(0);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
|
|
ANXDP_LNx_LINK_TRAINING_CTL(i), val);
|
|
}
|
|
|
|
if (anxdp_await_pll_lock(sc) != 0) {
|
|
device_printf(sc->sc_dev, "PLL lock timeout\n");
|
|
}
|
|
|
|
for (u_int i = 0; i < link->num_lanes; i++) {
|
|
training[i] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
|
|
DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
|
|
}
|
|
|
|
drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
|
|
link->num_lanes);
|
|
}
|
|
|
|
static void
|
|
anxdp_process_clock_recovery(struct anxdp_softc * const sc,
|
|
struct drm_dp_link * const link)
|
|
{
|
|
u_int i, tries;
|
|
uint8_t link_status[DP_LINK_STATUS_SIZE];
|
|
uint8_t training[4];
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_TRAINING_PTN_SET,
|
|
SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1);
|
|
drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
|
|
DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
|
|
|
|
tries = 0;
|
|
again:
|
|
if (tries++ >= 10) {
|
|
device_printf(sc->sc_dev, "cr fail\n");
|
|
return;
|
|
}
|
|
drm_dp_link_train_clock_recovery_delay(sc->sc_dpcd);
|
|
if (DP_LINK_STATUS_SIZE !=
|
|
drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) {
|
|
return;
|
|
}
|
|
if (!drm_dp_clock_recovery_ok(link_status, link->num_lanes)) {
|
|
goto cr_fail;
|
|
}
|
|
|
|
return;
|
|
|
|
cr_fail:
|
|
for (i = 0; i < link->num_lanes; i++) {
|
|
uint8_t vs, pe;
|
|
vs = drm_dp_get_adjust_request_voltage(link_status, i);
|
|
pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
|
|
training[i] = vs | pe;
|
|
}
|
|
for (i = 0; i < link->num_lanes; i++) {
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
|
|
ANXDP_LNx_LINK_TRAINING_CTL(i), training[i]);
|
|
}
|
|
drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
|
|
link->num_lanes);
|
|
goto again;
|
|
}
|
|
|
|
static void
|
|
anxdp_process_eq(struct anxdp_softc * const sc, struct drm_dp_link * const link)
|
|
{
|
|
u_int i, tries;
|
|
uint8_t link_status[DP_LINK_STATUS_SIZE];
|
|
uint8_t training[4];
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_TRAINING_PTN_SET,
|
|
SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2);
|
|
drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
|
|
DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2);
|
|
|
|
tries = 0;
|
|
again:
|
|
if (tries++ >= 10) {
|
|
device_printf(sc->sc_dev, "eq fail\n");
|
|
return;
|
|
}
|
|
drm_dp_link_train_channel_eq_delay(sc->sc_dpcd);
|
|
if (DP_LINK_STATUS_SIZE !=
|
|
drm_dp_dpcd_read_link_status(&sc->sc_dpaux, link_status)) {
|
|
return;
|
|
}
|
|
if (!drm_dp_channel_eq_ok(link_status, link->num_lanes)) {
|
|
goto eq_fail;
|
|
}
|
|
|
|
return;
|
|
|
|
eq_fail:
|
|
for (i = 0; i < link->num_lanes; i++) {
|
|
uint8_t vs, pe;
|
|
vs = drm_dp_get_adjust_request_voltage(link_status, i);
|
|
pe = drm_dp_get_adjust_request_pre_emphasis(link_status, i);
|
|
training[i] = vs | pe;
|
|
}
|
|
for (i = 0; i < link->num_lanes; i++) {
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
|
|
ANXDP_LNx_LINK_TRAINING_CTL(i), training[i]);
|
|
}
|
|
drm_dp_dpcd_write(&sc->sc_dpaux, DP_TRAINING_LANE0_SET, training,
|
|
link->num_lanes);
|
|
goto again;
|
|
}
|
|
|
|
static void
|
|
anxdp_train_link(struct anxdp_softc * const sc)
|
|
{
|
|
struct drm_dp_link link;
|
|
|
|
anxdp_macro_reset(sc);
|
|
|
|
if (0 != drm_dp_link_probe(&sc->sc_dpaux, &link)) {
|
|
device_printf(sc->sc_dev, "link probe failed\n");
|
|
return;
|
|
}
|
|
if (0 != drm_dp_link_power_up(&sc->sc_dpaux, &link))
|
|
return;
|
|
if (DP_RECEIVER_CAP_SIZE != drm_dp_dpcd_read(&sc->sc_dpaux, DP_DPCD_REV,
|
|
sc->sc_dpcd, DP_RECEIVER_CAP_SIZE))
|
|
return;
|
|
|
|
anxdp_link_start(sc, &link);
|
|
anxdp_process_clock_recovery(sc, &link);
|
|
anxdp_process_eq(sc, &link);
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_TRAINING_PTN_SET, 0);
|
|
drm_dp_dpcd_writeb(&sc->sc_dpaux, DP_TRAINING_PATTERN_SET,
|
|
DP_TRAINING_PATTERN_DISABLE);
|
|
|
|
}
|
|
|
|
static void
|
|
anxdp_bringup(struct anxdp_softc * const sc)
|
|
{
|
|
uint32_t val;
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_VIDEO_CTL_1);
|
|
val &= ~VIDEO_EN;
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_VIDEO_CTL_1, val);
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_VIDEO_CTL_1);
|
|
val &= ~VIDEO_MUTE;
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_VIDEO_CTL_1, val);
|
|
|
|
val = SW_FUNC_EN_N;
|
|
if (isrockchip(sc)) {
|
|
val |= RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N;
|
|
} else {
|
|
val |= MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
|
|
AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | HDCP_FUNC_EN_N;
|
|
}
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_1, val);
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_2,
|
|
SSC_FUNC_EN_N | AUX_FUNC_EN_N | SERDES_FIFO_FUNC_EN_N |
|
|
LS_CLK_DOMAIN_FUNC_EN_N);
|
|
|
|
delay(30);
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_M_AUD_GEN_FILTER_TH, 2);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_SOC_GENERAL_CTL, 0x101);
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_TX_SW_RESET,
|
|
RESET_DP_TX);
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_ANALOG_CTL_1,
|
|
TX_TERMINAL_CTRL_50_OHM);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_ANALOG_CTL_2,
|
|
SEL_24M | TX_DVDD_BIT_1_0625V);
|
|
if (isrockchip(sc)) {
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_PLL_REG_1,
|
|
REF_CLK_24M);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_PLL_REG_2,
|
|
0x95);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_PLL_REG_3,
|
|
0x40);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_PLL_REG_4,
|
|
0x58);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_PLL_REG_5,
|
|
0x22);
|
|
}
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_ANALOG_CTL_3,
|
|
DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_PLL_FILTER_CTL_1,
|
|
PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | TX_CUR1_2X | TX_CUR_16_MA);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_TX_AMP_TUNING_CTL, 0);
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_1);
|
|
val &= ~SW_FUNC_EN_N;
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_1, val);
|
|
|
|
anxdp_analog_power_up_all(sc);
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_COMMON_INT_STA_1,
|
|
PLL_LOCK_CHG);
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_DEBUG_CTL);
|
|
val &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_DEBUG_CTL, val);
|
|
|
|
if (anxdp_await_pll_lock(sc) != 0) {
|
|
device_printf(sc->sc_dev, "PLL lock timeout\n");
|
|
}
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_2);
|
|
val &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N |
|
|
AUX_FUNC_EN_N);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_2, val);
|
|
|
|
anxdp_init_hpd(sc);
|
|
anxdp_init_aux(sc);
|
|
}
|
|
|
|
static void
|
|
anxdp_bridge_enable(struct drm_bridge *bridge)
|
|
{
|
|
struct anxdp_softc * const sc = bridge->driver_private;
|
|
uint32_t val;
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_1);
|
|
if (isrockchip(sc)) {
|
|
val &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N);
|
|
} else {
|
|
val &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
|
|
val |= MASTER_VID_FUNC_EN_N;
|
|
}
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_FUNC_EN_1, val);
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_VIDEO_CTL_10);
|
|
val &= ~(SLAVE_I_SCAN_CFG|SLAVE_VSYNC_P_CFG|SLAVE_HSYNC_P_CFG);
|
|
if ((sc->sc_curmode.flags & DRM_MODE_FLAG_INTERLACE) != 0)
|
|
val |= SLAVE_I_SCAN_CFG;
|
|
if ((sc->sc_curmode.flags & DRM_MODE_FLAG_NVSYNC) != 0)
|
|
val |= SLAVE_VSYNC_P_CFG;
|
|
if ((sc->sc_curmode.flags & DRM_MODE_FLAG_NHSYNC) != 0)
|
|
val |= SLAVE_HSYNC_P_CFG;
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_VIDEO_CTL_10, val);
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_SOC_GENERAL_CTL,
|
|
AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE);
|
|
|
|
anxdp_train_link(sc);
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_VIDEO_CTL_1);
|
|
val |= VIDEO_EN;
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_VIDEO_CTL_1, val);
|
|
|
|
if (sc->sc_panel != NULL &&
|
|
sc->sc_panel->funcs != NULL &&
|
|
sc->sc_panel->funcs->enable != NULL)
|
|
sc->sc_panel->funcs->enable(sc->sc_panel);
|
|
#if ANXDP_AUDIO
|
|
|
|
if (sc->sc_connector.monitor_audio)
|
|
anxdp_audio_init(sc);
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
anxdp_bridge_pre_enable(struct drm_bridge *bridge)
|
|
{
|
|
}
|
|
|
|
static void
|
|
anxdp_bridge_disable(struct drm_bridge *bridge)
|
|
{
|
|
}
|
|
|
|
static void
|
|
anxdp_bridge_post_disable(struct drm_bridge *bridge)
|
|
{
|
|
}
|
|
|
|
static void
|
|
anxdp_bridge_mode_set(struct drm_bridge *bridge,
|
|
struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct anxdp_softc * const sc = bridge->driver_private;
|
|
|
|
sc->sc_curmode = *adjusted_mode;
|
|
}
|
|
|
|
static bool
|
|
anxdp_bridge_mode_fixup(struct drm_bridge *bridge,
|
|
const struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static const struct drm_bridge_funcs anxdp_bridge_funcs = {
|
|
.attach = anxdp_bridge_attach,
|
|
.enable = anxdp_bridge_enable,
|
|
.pre_enable = anxdp_bridge_pre_enable,
|
|
.disable = anxdp_bridge_disable,
|
|
.post_disable = anxdp_bridge_post_disable,
|
|
.mode_set = anxdp_bridge_mode_set,
|
|
.mode_fixup = anxdp_bridge_mode_fixup,
|
|
};
|
|
|
|
#if ANXDP_AUDIO
|
|
static int
|
|
anxdp_dai_set_format(audio_dai_tag_t dai, u_int format)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
anxdp_dai_add_device(audio_dai_tag_t dai, audio_dai_tag_t aux)
|
|
{
|
|
/* Not supported */
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
anxdp_audio_swvol_codec(audio_filter_arg_t *arg)
|
|
{
|
|
struct anxdp_softc * const sc = arg->context;
|
|
const aint_t *src;
|
|
aint_t *dst;
|
|
u_int sample_count;
|
|
u_int i;
|
|
|
|
src = arg->src;
|
|
dst = arg->dst;
|
|
sample_count = arg->count * arg->srcfmt->channels;
|
|
for (i = 0; i < sample_count; i++) {
|
|
aint2_t v = (aint2_t)(*src++);
|
|
v = v * sc->sc_swvol / 255;
|
|
*dst++ = (aint_t)v;
|
|
}
|
|
}
|
|
|
|
static int
|
|
anxdp_audio_set_format(void *priv, int setmode,
|
|
const audio_params_t *play, const audio_params_t *rec,
|
|
audio_filter_reg_t *pfil, audio_filter_reg_t *rfil)
|
|
{
|
|
struct anxdp_softc * const sc = priv;
|
|
|
|
pfil->codec = anxdp_audio_swvol_codec;
|
|
pfil->context = sc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
anxdp_audio_set_port(void *priv, mixer_ctrl_t *mc)
|
|
{
|
|
struct anxdp_softc * const sc = priv;
|
|
|
|
switch (mc->dev) {
|
|
case ANXDP_DAI_OUTPUT_MASTER_VOLUME:
|
|
case ANXDP_DAI_INPUT_DAC_VOLUME:
|
|
sc->sc_swvol = mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT];
|
|
return 0;
|
|
default:
|
|
return ENXIO;
|
|
}
|
|
}
|
|
|
|
static int
|
|
anxdp_audio_get_port(void *priv, mixer_ctrl_t *mc)
|
|
{
|
|
struct anxdp_softc * const sc = priv;
|
|
|
|
switch (mc->dev) {
|
|
case ANXDP_DAI_OUTPUT_MASTER_VOLUME:
|
|
case ANXDP_DAI_INPUT_DAC_VOLUME:
|
|
mc->un.value.level[AUDIO_MIXER_LEVEL_LEFT] = sc->sc_swvol;
|
|
mc->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = sc->sc_swvol;
|
|
return 0;
|
|
default:
|
|
return ENXIO;
|
|
}
|
|
}
|
|
|
|
static int
|
|
anxdp_audio_query_devinfo(void *priv, mixer_devinfo_t *di)
|
|
{
|
|
switch (di->index) {
|
|
case ANXDP_DAI_OUTPUT_CLASS:
|
|
di->mixer_class = di->index;
|
|
strcpy(di->label.name, AudioCoutputs);
|
|
di->type = AUDIO_MIXER_CLASS;
|
|
di->next = di->prev = AUDIO_MIXER_LAST;
|
|
return 0;
|
|
|
|
case ANXDP_DAI_INPUT_CLASS:
|
|
di->mixer_class = di->index;
|
|
strcpy(di->label.name, AudioCinputs);
|
|
di->type = AUDIO_MIXER_CLASS;
|
|
di->next = di->prev = AUDIO_MIXER_LAST;
|
|
return 0;
|
|
|
|
case ANXDP_DAI_OUTPUT_MASTER_VOLUME:
|
|
di->mixer_class = ANXDP_DAI_OUTPUT_CLASS;
|
|
strcpy(di->label.name, AudioNmaster);
|
|
di->un.v.delta = 1;
|
|
di->un.v.num_channels = 2;
|
|
strcpy(di->un.v.units.name, AudioNvolume);
|
|
di->type = AUDIO_MIXER_VALUE;
|
|
di->next = di->prev = AUDIO_MIXER_LAST;
|
|
return 0;
|
|
|
|
case ANXDP_DAI_INPUT_DAC_VOLUME:
|
|
di->mixer_class = ANXDP_DAI_INPUT_CLASS;
|
|
strcpy(di->label.name, AudioNdac);
|
|
di->un.v.delta = 1;
|
|
di->un.v.num_channels = 2;
|
|
strcpy(di->un.v.units.name, AudioNvolume);
|
|
di->type = AUDIO_MIXER_VALUE;
|
|
di->next = di->prev = AUDIO_MIXER_LAST;
|
|
return 0;
|
|
|
|
default:
|
|
return ENXIO;
|
|
}
|
|
}
|
|
|
|
static const struct audio_hw_if anxdp_dai_hw_if = {
|
|
.set_format = anxdp_audio_set_format,
|
|
.set_port = anxdp_audio_set_port,
|
|
.get_port = anxdp_audio_get_port,
|
|
.query_devinfo = anxdp_audio_query_devinfo,
|
|
};
|
|
#endif
|
|
|
|
static ssize_t
|
|
anxdp_dp_aux_transfer(struct drm_dp_aux *dpaux, struct drm_dp_aux_msg *dpmsg)
|
|
{
|
|
struct anxdp_softc * const sc = container_of(dpaux, struct anxdp_softc,
|
|
sc_dpaux);
|
|
size_t loop_timeout = 0;
|
|
uint32_t val;
|
|
size_t i;
|
|
ssize_t ret = 0;
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_BUFFER_DATA_CTL,
|
|
BUF_CLR);
|
|
|
|
val = AUX_LENGTH(dpmsg->size);
|
|
if ((dpmsg->request & DP_AUX_I2C_MOT) != 0)
|
|
val |= AUX_TX_COMM_MOT;
|
|
|
|
switch (dpmsg->request & ~DP_AUX_I2C_MOT) {
|
|
case DP_AUX_I2C_WRITE:
|
|
break;
|
|
case DP_AUX_I2C_READ:
|
|
val |= AUX_TX_COMM_READ;
|
|
break;
|
|
case DP_AUX_NATIVE_WRITE:
|
|
val |= AUX_TX_COMM_DP;
|
|
break;
|
|
case DP_AUX_NATIVE_READ:
|
|
val |= AUX_TX_COMM_READ | AUX_TX_COMM_DP;
|
|
break;
|
|
}
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_CH_CTL_1, val);
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_ADDR_7_0,
|
|
AUX_ADDR_7_0(dpmsg->address));
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_ADDR_15_8,
|
|
AUX_ADDR_15_8(dpmsg->address));
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_ADDR_19_16,
|
|
AUX_ADDR_19_16(dpmsg->address));
|
|
|
|
if (!(dpmsg->request & DP_AUX_I2C_READ)) {
|
|
for (i = 0; i < dpmsg->size; i++) {
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
|
|
ANXDP_BUF_DATA(i),
|
|
((const uint8_t *)(dpmsg->buffer))[i]);
|
|
ret++;
|
|
}
|
|
}
|
|
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_CH_CTL_2,
|
|
AUX_EN | ((dpmsg->size == 0) ? ADDR_ONLY : 0));
|
|
|
|
loop_timeout = 0;
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_CH_CTL_2);
|
|
while ((val & AUX_EN) != 0) {
|
|
if (++loop_timeout > 20000) {
|
|
ret = -ETIMEDOUT;
|
|
goto out;
|
|
}
|
|
delay(25);
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
|
|
ANXDP_AUX_CH_CTL_2);
|
|
}
|
|
|
|
loop_timeout = 0;
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_DP_INT_STA);
|
|
while (!(val & RPLY_RECEIV)) {
|
|
if (++loop_timeout > 2000) {
|
|
ret = -ETIMEDOUT;
|
|
goto out;
|
|
}
|
|
delay(10);
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
|
|
ANXDP_DP_INT_STA);
|
|
}
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_DP_INT_STA,
|
|
RPLY_RECEIV);
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_DP_INT_STA);
|
|
if ((val & AUX_ERR) != 0) {
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_DP_INT_STA,
|
|
AUX_ERR);
|
|
ret = -EREMOTEIO;
|
|
goto out;
|
|
}
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_CH_STA);
|
|
if (AUX_STATUS(val) != 0) {
|
|
ret = -EREMOTEIO;
|
|
goto out;
|
|
}
|
|
|
|
if ((dpmsg->request & DP_AUX_I2C_READ)) {
|
|
for (i = 0; i < dpmsg->size; i++) {
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
|
|
ANXDP_BUF_DATA(i));
|
|
((uint8_t *)(dpmsg->buffer))[i] = val & 0xffU;
|
|
ret++;
|
|
}
|
|
}
|
|
|
|
val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_AUX_RX_COMM);
|
|
if (val == AUX_RX_COMM_AUX_DEFER)
|
|
dpmsg->reply = DP_AUX_NATIVE_REPLY_DEFER;
|
|
else if (val == AUX_RX_COMM_I2C_DEFER)
|
|
dpmsg->reply = DP_AUX_I2C_REPLY_DEFER;
|
|
else if ((dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE ||
|
|
(dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ)
|
|
dpmsg->reply = DP_AUX_I2C_REPLY_ACK;
|
|
else if ((dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE ||
|
|
(dpmsg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ)
|
|
dpmsg->reply = DP_AUX_NATIVE_REPLY_ACK;
|
|
|
|
out:
|
|
if (ret < 0)
|
|
anxdp_init_aux(sc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
anxdp_dpms(struct anxdp_softc *sc, int mode)
|
|
{
|
|
switch (mode) {
|
|
case DRM_MODE_DPMS_ON:
|
|
pmf_event_inject(NULL, PMFE_DISPLAY_ON);
|
|
break;
|
|
case DRM_MODE_DPMS_STANDBY:
|
|
case DRM_MODE_DPMS_SUSPEND:
|
|
case DRM_MODE_DPMS_OFF:
|
|
pmf_event_inject(NULL, PMFE_DISPLAY_OFF);
|
|
break;
|
|
}
|
|
}
|
|
|
|
int
|
|
anxdp_attach(struct anxdp_softc *sc)
|
|
{
|
|
#if ANXDP_AUDIO
|
|
sc->sc_swvol = 255;
|
|
|
|
/*
|
|
* Initialize audio DAI
|
|
*/
|
|
sc->sc_dai.dai_set_format = anxdp_dai_set_format;
|
|
sc->sc_dai.dai_add_device = anxdp_dai_add_device;
|
|
sc->sc_dai.dai_hw_if = &anxdp_dai_hw_if;
|
|
sc->sc_dai.dai_dev = sc->sc_dev;
|
|
sc->sc_dai.dai_priv = sc;
|
|
#endif
|
|
|
|
sc->sc_dpaux.name = "DP Aux";
|
|
sc->sc_dpaux.transfer = anxdp_dp_aux_transfer;
|
|
sc->sc_dpaux.dev = sc->sc_dev;
|
|
if (drm_dp_aux_register(&sc->sc_dpaux) != 0) {
|
|
device_printf(sc->sc_dev, "registering DP Aux failed\n");
|
|
}
|
|
|
|
anxdp_bringup(sc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
anxdp_bind(struct anxdp_softc *sc, struct drm_encoder *encoder)
|
|
{
|
|
int error;
|
|
|
|
sc->sc_bridge.driver_private = sc;
|
|
sc->sc_bridge.funcs = &anxdp_bridge_funcs;
|
|
sc->sc_bridge.encoder = encoder;
|
|
|
|
error = drm_bridge_attach(encoder->dev, &sc->sc_bridge);
|
|
if (error != 0)
|
|
return EIO;
|
|
|
|
encoder->bridge = &sc->sc_bridge;
|
|
|
|
if (sc->sc_panel != NULL && sc->sc_panel->funcs != NULL && sc->sc_panel->funcs->prepare != NULL)
|
|
sc->sc_panel->funcs->prepare(sc->sc_panel);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void anxdp0_dump(void);
|
|
|
|
void
|
|
anxdp0_dump(void)
|
|
{
|
|
extern struct cfdriver anxdp_cd;
|
|
struct anxdp_softc * const sc = device_lookup_private(&anxdp_cd, 0);
|
|
size_t i;
|
|
|
|
if (sc == NULL)
|
|
return;
|
|
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_1,
|
|
bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_1));
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_2,
|
|
bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_2));
|
|
bus_space_write_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_3,
|
|
bus_space_read_4(sc->sc_bst, sc->sc_bsh, ANXDP_SYS_CTL_3));
|
|
for (i = 0x000; i < 0xb00; i += 4)
|
|
device_printf(sc->sc_dev, "%03zx 0x%08x\n", i,
|
|
bus_space_read_4(sc->sc_bst, sc->sc_bsh, i));
|
|
}
|