2bc996b0bc
interrupt code for the IQ80310 board support package. XXX The Integrator board support package still uses the old-style arm32 interrupt code, so some compatibility hacks have been added for it. When the Integrator uses new-style interrupts, those hacks can go away.
141 lines
4.2 KiB
C
141 lines
4.2 KiB
C
/* $NetBSD: plcom_ifpga.c,v 1.2 2002/01/30 03:59:41 thorpej Exp $ */
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/*
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* Copyright (c) 2001 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Interface to plcom (PL010) serial driver. */
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#include <sys/types.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <sys/param.h>
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#include <sys/malloc.h>
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#include <sys/termios.h>
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#include <machine/intr.h>
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#include <evbarm/ifpga/irqhandler.h> /* XXX XXX XXX */
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#include <machine/bus.h>
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#include <evbarm/dev/plcomreg.h>
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#include <evbarm/dev/plcomvar.h>
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#include <evbarm/ifpga/plcom_ifpgavar.h>
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#include <evbarm/ifpga/ifpgareg.h>
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#include <evbarm/ifpga/ifpgavar.h>
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static int plcom_ifpga_match(struct device *, struct cfdata *, void *);
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static void plcom_ifpga_attach(struct device *, struct device *, void *);
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static void plcom_ifpga_set_mcr(void *, int, u_int);
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struct cfattach plcom_ifpga_ca = {
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sizeof(struct plcom_softc), plcom_ifpga_match, plcom_ifpga_attach
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};
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static int
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plcom_ifpga_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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if (strcmp(cf->cf_driver->cd_name, "plcom") == 0)
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return 1;
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return 0;
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}
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static void
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plcom_ifpga_attach(struct device *parent, struct device *self, void *aux)
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{
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struct plcom_ifpga_softc *isc = (struct plcom_ifpga_softc *)self;
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struct plcom_softc *sc = &isc->sc_plcom;
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struct ifpga_attach_args *ifa = aux;
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char *irqname;
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isc->sc_iot = ifa->ifa_iot;
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isc->sc_ioh = ifa->ifa_sc_ioh;
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sc->sc_iounit = sc->sc_dev.dv_unit;
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sc->sc_frequency = IFPGA_UART_CLK;
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sc->sc_iot = ifa->ifa_iot;
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sc->sc_hwflags = 0;
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sc->sc_swflags = 0;
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sc->sc_set_mcr = plcom_ifpga_set_mcr;
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sc->sc_set_mcr_arg = (void *)isc;
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if (bus_space_map(ifa->ifa_iot, ifa->ifa_addr, PLCOM_UART_SIZE, 0,
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&sc->sc_ioh)) {
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printf("%s: unable to map device\n", sc->sc_dev.dv_xname);
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return;
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}
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plcom_attach_subr(sc);
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irqname = malloc(sizeof("uart") + 2, M_DEVBUF, M_WAITOK);
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sprintf(irqname, "uart%d", sc->sc_dev.dv_unit);
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isc->sc_ih = intr_claim(ifa->ifa_irq, IPL_SERIAL, irqname, plcomintr,
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sc);
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if (isc->sc_ih == NULL)
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panic("%s: cannot install interrupt handler\n",
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sc->sc_dev.dv_xname);
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}
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static void plcom_ifpga_set_mcr(void *aux, int unit, u_int mcr)
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{
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struct plcom_ifpga_softc *isc = (struct plcom_ifpga_softc *)aux;
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u_int set, clr;
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set = clr = 0;
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switch (unit) {
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case 0:
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if (mcr & MCR_RTS)
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set |= IFPGA_SC_CTRL_UART0RTS;
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else
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clr |= IFPGA_SC_CTRL_UART0RTS;
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if (mcr & MCR_DTR)
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set |= IFPGA_SC_CTRL_UART0DTR;
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else
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clr |= IFPGA_SC_CTRL_UART0DTR;
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case 1:
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if (mcr & MCR_RTS)
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set |= IFPGA_SC_CTRL_UART1RTS;
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else
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clr |= IFPGA_SC_CTRL_UART1RTS;
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if (mcr & MCR_DTR)
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set |= IFPGA_SC_CTRL_UART1DTR;
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else
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clr |= IFPGA_SC_CTRL_UART1DTR;
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default:
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return;
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}
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if (set)
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bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLS,
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set);
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if (clr)
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bus_space_write_1(isc->sc_iot, isc->sc_ioh, IFPGA_SC_CTRLC,
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clr);
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}
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