264 lines
12 KiB
C
264 lines
12 KiB
C
/* $NetBSD: ahcisatareg.h,v 1.3 2007/12/25 18:33:37 perry Exp $ */
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/*
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* Copyright (c) 2006 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* SATA AHCI v1.0 register defines */
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/* misc defines */
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#define AHCI_MAX_PORTS 32
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#define AHCI_MAX_CMDS 32
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/* in-memory structures used by the controller */
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/* physical region descriptor: points to a region of data (max 4MB) */
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struct ahci_dma_prd {
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u_int32_t prd_dba; /* data base address (64 bits) */
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u_int32_t prd_dbau;
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u_int32_t prd_res; /* reserved */
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u_int32_t prd_dbc; /* data byte count */
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#define AHCI_PRD_DBC_MASK 0x003fffff
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#define AHCI_PRD_DBC_IPC 0x80000000 /* interrupt on completion */
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} __packed;
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#define AHCI_NPRD ((MAXPHYS/PAGE_SIZE) + 1)
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/* command table: describe a command to send to drive */
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struct ahci_cmd_tbl {
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u_int8_t cmdt_cfis[64]; /* command FIS */
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u_int8_t cmdt_acmd[16]; /* ATAPI command */
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u_int8_t cmdt_res[48]; /* reserved */
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struct ahci_dma_prd cmdt_prd[1]; /* extended to AHCI_NPRD */
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} __packed;
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#define AHCI_CMDTBL_ALIGN 0x7f
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#define AHCI_CMDTBL_SIZE ((sizeof(struct ahci_cmd_tbl) + \
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(sizeof(struct ahci_dma_prd) * (AHCI_NPRD - 1)) + (AHCI_CMDTBL_ALIGN)) \
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& ~AHCI_CMDTBL_ALIGN)
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/*
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* command header: points to a command table. The command list is an array
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* of theses.
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*/
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struct ahci_cmd_header {
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u_int16_t cmdh_flags;
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#define AHCI_CMDH_F_PMP_MASK 0xf000 /* port multiplier port */
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#define AHCI_CMDH_F_PMP_SHIFT 12
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#define AHCI_CMDH_F_CBSY 0x0400 /* clear BSY on R_OK */
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#define AHCI_CMDH_F_BIST 0x0200 /* BIST FIS */
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#define AHCI_CMDH_F_RST 0x0100 /* Reset FIS */
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#define AHCI_CMDH_F_PRF 0x0080 /* prefectchable */
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#define AHCI_CMDH_F_WR 0x0040 /* write */
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#define AHCI_CMDH_F_A 0x0020 /* ATAPI */
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#define AHCI_CMDH_F_CFL_MASK 0x001f /* command FIS length (in dw) */
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#define AHCI_CMDH_F_CFL_SHIFT 0
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u_int16_t cmdh_prdtl; /* number of cmdt_prd */
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u_int32_t cmdh_prdbc; /* physical region descriptor byte count */
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u_int32_t cmdh_cmdtba; /* phys. addr. of cmd_tbl */
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u_int32_t cmdh_cmdtbau; /* (64bits, 128bytes aligned) */
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u_int32_t cmdh_res[4]; /* reserved */
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} __packed;
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#define AHCI_CMDH_SIZE (sizeof(struct ahci_cmd_header) * AHCI_MAX_CMDS)
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/* received FIS: where the HBA stores various type of FIS it receives */
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struct ahci_r_fis {
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u_int8_t rfis_dsfis[32]; /* DMA setup FIS */
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u_int8_t rfis_psfis[32]; /* PIO setup FIS */
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u_int8_t rfis_rfis[24]; /* D2H register FIS */
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u_int8_t rfis_sdbfis[8]; /* set device bit FIS */
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u_int8_t rfis_ukfis[64]; /* unknown FIS */
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u_int8_t rfis_res[96];
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} __packed;
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#define AHCI_RFIS_SIZE (sizeof(struct ahci_r_fis))
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/* PCI registers */
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/* class Mass storage, subclass SATA, interface AHCI */
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#define PCI_INTERFACE_SATA_AHCI 0x01
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#define AHCI_PCI_ABAR 0x24 /* native ACHI registers (memory mapped) */
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/* ABAR registers */
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/* Global registers */
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#define AHCI_CAP 0x00 /* HBA capabilities */
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#define AHCI_CAP_NPMASK 0x0000001f /* Number of ports */
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#define AHCI_CAP_XS 0x00000020 /* External SATA */
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#define AHCI_CAP_EM 0x00000040 /* Enclosure Management */
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#define AHCI_CAP_CCC 0x00000080 /* command completion coalescing */
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#define AHCI_CAP_NCS 0x00001f00 /* number of command slots */
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#define AHCI_CAP_PS 0x00002000 /* Partial State */
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#define AHCI_CAP_SS 0x00004000 /* Slumber State */
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#define AHCI_CAP_PMD 0x00008000 /* PIO multiple DRQ blocks */
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#define AHCI_CAP_FBS 0x00010000 /* FIS-Based switching */
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#define AHCI_CAP_SPM 0x00020000 /* Port multipliers */
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#define AHCI_CAP_SAM 0x00040000 /* AHCI-only */
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#define AHCI_CAP_NZO 0x00080000 /* Non-zero DMA offset (reserved) */
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#define AHCI_CAP_IS 0x00f00000 /* Interface speed */
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#define AHCI_CAP_IS_GEN1 0x00100000 /* 1.5 GB/s */
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#define AHCI_CAP_IS_GEN2 0x00200000 /* 1.5 and 3 GB/s */
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#define AHCI_CAP_CLO 0x01000000 /* Command list override */
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#define AHCI_CAP_AL 0x02000000 /* Single Activitly LED */
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#define AHCI_CAP_ALP 0x04000000 /* Agressive link power management */
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#define AHCI_CAP_SSU 0x08000000 /* Staggered spin-up */
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#define AHCI_CAP_MPS 0x10000000 /* Mechanical swicth */
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#define AHCI_CAP_NTF 0x20000000 /* Snotification */
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#define AHCI_CAP_NCQ 0x40000000 /* Native command queuing */
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#define AHCI_CAP_64BIT 0x80000000 /* 64bit addresses */
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#define AHCI_GHC 0x04 /* HBA control */
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#define AHCI_GHC_HR 0x00000001 /* HBA reset */
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#define AHCI_GHC_IE 0x00000002 /* Interrupt enable */
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#define AHCI_GHC_MRSM 0x00000004 /* MSI revert to single message */
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#define AHCI_GHC_AE 0x80000000 /* AHCI enable */
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#define AHCI_IS 0x08 /* Interrupt status register: one bit per port */
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#define AHCI_PI 0x0c /* Port implemented: one bit per port */
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#define AHCI_VS 0x10 /* AHCI version */
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#define AHCI_VS_10 0x00010000 /* AHCI spec 1.0 */
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#define AHCI_VS_11 0x00010100 /* AHCI spec 1.1 */
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#define AHCI_CC_CTL 0x14 /* command completion coalescing control */
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#define AHCI_CC_TV_MASK 0xffff0000 /* timeout value */
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#define AHCI_CC_TV_SHIFT 16
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#define AHCI_CC_CC_MASK 0x0000ff00 /* command completion */
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#define AHCI_CC_CC_SHIFT 8
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#define AHCI_CC_INT_MASK 0x000000f8 /* interrupt */
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#define AHCI_CC_INT_SHIFT 3
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#define AHCI_CC_EN 0x000000001 /* enable */
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#define AHCI_CC_PORTS 0x18 /* command completion coalescing ports (1b/port */
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#define AHCI_EM_LOC 0x1c /* enclosure managemement location */
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#define AHCI_EML_OFF_MASK 0xffff0000 /* offset in ABAR */
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#define AHCI_EML_OFF_SHIFT 16
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#define AHCI_EML_SZ_MASK 0x0000ffff /* offset in ABAR */
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#define AHCI_EML_SZ_SHIFT 0
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#define AHCI_EM_CTL 0x20 /* enclosure management control */
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#define AHCI_EMC_PM 0x08000000 /* port multiplier support */
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#define AHCI_EMC_ALHD 0x04000000 /* activity LED hardware driven */
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#define AHCI_EMC_XMIT 0x02000000 /* tramsit messages only */
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#define AHCI_EMC_SMB 0x01000000 /* single message buffer */
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#define AHCI_EMC_SGPIO 0x00080000 /* enclosure management messages */
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#define AHCI_EMC_SES2 0x00040000 /* SeS-2 messages */
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#define AHCI_EMC_SAF 0x00020000 /* SAF_TE messages */
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#define AHCI_EMC_LED 0x00010000 /* LED messages */
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#define AHCI_EMC_RST 0x00000200 /* Reset */
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#define AHCI_EMC_TM 0x00000100 /* Transmit message */
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#define AHCI_EMC_MR 0x00000001 /* Message received */
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/* Per-port registers */
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#define AHCI_P_OFFSET(port) (0x80 * (port))
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#define AHCI_P_CLB(p) (0x100 + AHCI_P_OFFSET(p)) /* command list addr */
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#define AHCI_P_CLBU(p) (0x104 + AHCI_P_OFFSET(p)) /* command list addr */
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#define AHCI_P_FB(p) (0x108 + AHCI_P_OFFSET(p)) /* FIS addr */
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#define AHCI_P_FBU(p) (0x10c + AHCI_P_OFFSET(p)) /* FIS addr */
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#define AHCI_P_IS(p) (0x110 + AHCI_P_OFFSET(p)) /* Interrupt status */
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#define AHCI_P_IE(p) (0x114 + AHCI_P_OFFSET(p)) /* Interrupt enable */
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#define AHCI_P_IX_CPDS 0x80000000 /* Cold port detect */
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#define AHCI_P_IX_TFES 0x40000000 /* Task file error */
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#define AHCI_P_IX_HBFS 0x20000000 /* Host bus fatal error */
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#define AHCI_P_IX_HBDS 0x10000000 /* Host bus data error */
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#define AHCI_P_IX_IFS 0x08000000 /* Interface fatal error */
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#define AHCI_P_IX_INFS 0x04000000 /* Interface non-fatal error */
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#define AHCI_P_IX_OFS 0x01000000 /* Overflow */
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#define AHCI_P_IX_IPMS 0x00800000 /* Incorrect port multiplier */
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#define AHCI_P_IX_PRCS 0x00400000 /* Phy Ready change */
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#define AHCI_P_IX_DMPS 0x00000080 /* Device Mechanical Presence */
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#define AHCI_P_IX_PCS 0x00000040 /* port Connect change */
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#define AHCI_P_IX_DPS 0x00000020 /* dexcriptor processed */
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#define AHCI_P_IX_UFS 0x00000010 /* Unknown FIS */
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#define AHCI_P_IX_SDBS 0x00000008 /* Set device bit */
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#define AHCI_P_IX_DSS 0x00000004 /* DMA setup FIS */
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#define AHCI_P_IX_PSS 0x00000002 /* PIO setup FIS */
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#define AHCI_P_IX_DHRS 0x00000001 /* Device to Host FIS */
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#define AHCI_P_CMD(p) (0x118 + AHCI_P_OFFSET(p)) /* Port command/status */
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#define AHCI_P_CMD_ICC_MASK 0xf0000000 /* Interface Comm. Control */
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#define AHCI_P_CMD_ICC_SL 0x60000000 /* State slumber */
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#define AHCI_P_CMD_ICC_PA 0x20000000 /* State partial */
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#define AHCI_P_CMD_ICC_AC 0x10000000 /* State active */
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#define AHCI_P_CMD_ICC_NO 0x00000000 /* State idle/NOP */
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#define AHCI_P_CMD_ASP 0x08000000 /* Agressive Slumber/Partial */
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#define AHCI_P_CMD_ALPE 0x04000000 /* Agressive link power management */
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#define AHCI_P_CMD_DLAE 0x02000000 /* drive LED on ATAPI */
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#define AHCI_P_CMD_ATAP 0x01000000 /* Device is ATAPI */
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#define AHCI_P_CMD_ESP 0x00200000 /* external SATA port */
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#define AHCI_P_CMD_CPD 0x00100000 /* Cold presence detection */
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#define AHCI_P_CMD_MPSP 0x00080000 /* Mechanical switch attached */
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#define AHCI_P_CMD_HPCP 0x00040000 /* hot-plug capable */
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#define AHCI_P_CMD_PMA 0x00020000 /* port multiplier attached */
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#define AHCI_P_CMD_CPS 0x00010000 /* cold presence state */
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#define AHCI_P_CMD_CR 0x00008000 /* command list running */
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#define AHCI_P_CMD_FR 0x00004000 /* FIS receive running */
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#define AHCI_P_CMD_MPSS 0x00002000 /* mechanical switch state */
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#define AHCI_P_CMD_CCS_MASK 0x00001f00 /* current command slot */
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#define AHCI_P_CMD_CCS_SHIFT 12
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#define AHCI_P_CMD_FRE 0x00000010 /* FIS receive enable */
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#define AHCI_P_CMD_CLO 0x00000008 /* command list override */
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#define AHCI_P_CMD_POD 0x00000004 /* power on device */
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#define AHCI_P_CMD_SUD 0x00000002 /* spin up device */
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#define AHCI_P_CMD_ST 0x00000001 /* start */
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#define AHCI_P_TFD(p) (0x120 + AHCI_P_OFFSET(p)) /* Port task file data */
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#define AHCI_P_TFD_ERR_MASK 0x0000ff00 /* error register */
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#define AHCI_P_TFD_ERR_SHIFT 8
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#define AHCI_P_TFD_ST 0x000000ff /* status register */
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#define AHCI_P_TFD_ST_SHIFT 0
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#define AHCI_P_SIG(p) (0x124 + AHCI_P_OFFSET(p)) /* device signature */
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#define AHCI_P_SIG_LBAH_MASK 0xff000000
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#define AHCI_P_SIG_LBAH_SHIFT 24
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#define AHCI_P_SIG_LBAM_MASK 0x00ff0000
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#define AHCI_P_SIG_LBAM_SHIFT 16
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#define AHCI_P_SIG_LBAL_MASK 0x0000ff00
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#define AHCI_P_SIG_LBAL_SHIFT 8
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#define AHCI_P_SIG_SC_MASK 0x000000ff
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#define AHCI_P_SIG_SC_SHIFT 8
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#define AHCI_P_SSTS(p) (0x128 + AHCI_P_OFFSET(p)) /* Serial ATA status */
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#define AHCI_P_SCTL(p) (0x12c + AHCI_P_OFFSET(p)) /* Serial ATA control */
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#define AHCI_P_SERR(p) (0x130 + AHCI_P_OFFSET(p)) /* Serial ATA error */
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#define AHCI_P_SACT(p) (0x134 + AHCI_P_OFFSET(p)) /* Serial ATA active */
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/* one bit per tag/command slot */
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#define AHCI_P_CI(p) (0x138 + AHCI_P_OFFSET(p)) /* Command issued */
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/* one bit per tag/command slot */
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#define AHCI_P_FNTF(p) (0x13c + AHCI_P_OFFSET(p)) /* SNotification */
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/* one bit per port */
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