137 lines
5.0 KiB
C
137 lines
5.0 KiB
C
/* $NetBSD: amlogic_crureg.h,v 1.7 2015/03/08 12:44:55 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_AMLOGIC_CRUREG_H
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#define _ARM_AMLOGIC_CRUREG_H
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#define CBUS_REG(n) ((n) << 2)
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#define EE_CLK_GATING0_REG CBUS_REG(0x1050)
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#define EE_CLK_GATING1_REG CBUS_REG(0x1051)
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#define EE_CLK_GATING2_REG CBUS_REG(0x1052)
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#define EE_CLK_GATING3_REG CBUS_REG(0x1054)
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#define EE_CLK_GATING0_SDIO __BIT(17)
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#define EE_CLK_GATING0_SDHC __BIT(14)
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#define EE_CLK_GATING0_RNG __BIT(12)
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#define EE_CLK_GATING1_USB_GENERAL __BIT(26)
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#define EE_CLK_GATING1_USB1 __BIT(22)
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#define EE_CLK_GATING1_USB0 __BIT(21)
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#define EE_CLK_GATING1_ETHERNET __BIT(3)
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#define EE_CLK_GATING2_USB0_TO_DDR __BIT(9)
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#define EE_CLK_GATING2_USB1_TO_DDR __BIT(8)
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#define EE_CLK_GATING3_RNG __BIT(21)
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#define HHI_SYS_CPU_CLK_CNTL1_REG CBUS_REG(0x1057)
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#define HHI_SYS_CPU_CLK_CNTL1_SDIV __BITS(29,20)
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#define HHI_SYS_CPU_CLK_CNTL1_PERIPH_CLK_MUX __BITS(8,6)
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#define HHI_SYS_CPU_CLK_CNTL0_REG CBUS_REG(0x1067)
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#define HHI_SYS_CPU_CLK_CNTL0_CLKSEL __BIT(7)
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#define HHI_SYS_CPU_CLK_CNTL0_SOUTSEL __BITS(3,2)
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#define HHI_SYS_CPU_CLK_CNTL0_PLLSEL __BITS(1,0)
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#define HHI_SYS_PLL_CNTL_REG CBUS_REG(0x10c0)
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#define HHI_SYS_PLL_CNTL_MUL __BITS(8,0)
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#define HHI_SYS_PLL_CNTL_DIV __BITS(14,9)
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#define HHI_SYS_PLL_CNTL_OD __BITS(17,16)
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#define HHI_MPLL_CNTL_REG CBUS_REG(0x10a0)
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#define HHI_MPLL_CNTL_MUL __BITS(8,0)
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#define HHI_MPLL_CNTL_DIV __BITS(13,9)
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#define HHI_MPLL_CNTL_OD __BITS(17,16)
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#define RESET1_REG CBUS_REG(0x1102)
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#define RESET1_USB __BIT(2)
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#define PREG_CTLREG0_ADDR_REG CBUS_REG(0x2000)
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#define PREG_CTLREG0_ADDR_CLKRATE __BITS(9,4)
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#define PREG_PAD_GPIO0_EN_N_REG CBUS_REG(0x200c)
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#define PERIPHS_PIN_MUX_0_REG CBUS_REG(0x202c)
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#define PERIPHS_PIN_MUX_1_REG CBUS_REG(0x202d)
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#define PERIPHS_PIN_MUX_2_REG CBUS_REG(0x202e)
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#define PERIPHS_PIN_MUX_3_REG CBUS_REG(0x202f)
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#define PERIPHS_PIN_MUX_4_REG CBUS_REG(0x2030)
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#define PERIPHS_PIN_MUX_5_REG CBUS_REG(0x2031)
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#define PERIPHS_PIN_MUX_6_REG CBUS_REG(0x2032)
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#define PERIPHS_PIN_MUX_7_REG CBUS_REG(0x2033)
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#define PERIPHS_PIN_MUX_8_REG CBUS_REG(0x2034)
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#define PERIPHS_PIN_MUX_9_REG CBUS_REG(0x2035)
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#define PAD_PULL_UP_6_REG CBUS_REG(0x2039)
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#define PAD_PULL_UP_0_REG CBUS_REG(0x203a)
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#define PAD_PULL_UP_1_REG CBUS_REG(0x203b)
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#define PAD_PULL_UP_2_REG CBUS_REG(0x203c)
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#define PAD_PULL_UP_3_REG CBUS_REG(0x203d)
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#define PAD_PULL_UP_4_REG CBUS_REG(0x203e)
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#define PAD_PULL_UP_5_REG CBUS_REG(0x203f)
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#define RAND64_ADDR0_REG CBUS_REG(0x2040)
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#define RAND64_ADDR1_REG CBUS_REG(0x2041)
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#define PAD_PULL_UP_EN_0_REG CBUS_REG(0x2048)
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#define PAD_PULL_UP_EN_1_REG CBUS_REG(0x2049)
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#define PAD_PULL_UP_EN_2_REG CBUS_REG(0x204a)
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#define PAD_PULL_UP_EN_3_REG CBUS_REG(0x204b)
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#define PAD_PULL_UP_EN_4_REG CBUS_REG(0x204c)
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#define PAD_PULL_UP_EN_5_REG CBUS_REG(0x204d)
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#define PAD_PULL_UP_EN_6_REG CBUS_REG(0x204e)
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#define PREI_USB_PHY_A_CFG_REG CBUS_REG(0x2200)
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#define PREI_USB_PHY_A_CTRL_REG CBUS_REG(0x2201)
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#define PREI_USB_PHY_A_ADP_BC_REG CBUS_REG(0x2203)
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#define PREI_USB_PHY_B_CFG_REG CBUS_REG(0x2208)
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#define PREI_USB_PHY_B_CTRL_REG CBUS_REG(0x2209)
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#define PREI_USB_PHY_B_ADP_BC_REG CBUS_REG(0x220b)
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#define PREI_USB_PHY_CFG_CLK_32K_ALT_SEL __BIT(15)
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#define PREI_USB_PHY_CTRL_FSEL __BITS(24,22)
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#define PREI_USB_PHY_CTRL_FSEL_24M 5
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#define PREI_USB_PHY_CTRL_FSEL_12M 2
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#define PREI_USB_PHY_CTRL_POR __BIT(15)
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#define PREI_USB_PHY_CTRL_CLK_DET __BIT(8)
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#define PREI_USB_PHY_ADP_BC_ACA_FLOATING __BIT(26)
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#define PREI_USB_PHY_ADP_BC_ACA_ENABLE __BIT(16)
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#define WATCHDOG_TC_REG CBUS_REG(0x2640)
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#define WATCHDOG_TC_CPUS __BITS(27,24)
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#define WATCHDOG_TC_ENABLE __BIT(19)
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#define WATCHDOG_TC_TCNT __BITS(15,0)
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#define WATCHDOG_RESET_REG CBUS_REG(0x2641)
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#define WATCHDOG_RESET_COUNT __BITS(15,0)
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#endif /* _ARM_AMLOGIC_CRUREG_H */
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