74 lines
3.1 KiB
C
74 lines
3.1 KiB
C
/* $NetBSD: pciide_sis_reg.h,v 1.5 1998/12/04 17:30:55 drochner Exp $ */
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/*
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* Copyright (c) 1998 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Registers definitions for SiS SiS5597/98 PCI IDE controller.
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* Available from http://www.sis.com.tw/html/databook.html
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*/
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/* IDE timing control registers (32 bits) */
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#define SIS_TIM(channel) (0x40 + (channel * 4))
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#define SIS_TIM_REC_OFF(drive) (16 * (drive))
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#define SIS_TIM_ACT_OFF(drive) (8 + 16 * (drive))
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#define SIS_TIM_UDMA_TIME_OFF(drive) (13 + 16 * (drive))
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#define SIS_TIM_UDMA_EN(drive) (1 << (15 + 16 * (drive)))
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/* IDE general control register 0 (8 bits) */
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#define SIS_CTRL0 0x4a
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#define SIS_CTRL0_PCIBURST 0x80
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#define SIS_CTRL0_FAST_PW 0x20
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#define SIS_CTRL0_BO 0x08
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#define SIS_CTRL0_CHAN0_EN 0x02 /* manual (v2.0) is wrong!!! */
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#define SIS_CTRL0_CHAN1_EN 0x04 /* manual (v2.0) is wrong!!! */
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/* IDE general control register 1 (8 bits) */
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#define SIS_CTRL1 0x4b
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#define SIS_CTRL1_POSTW_EN(chan, drv) (0x10 << ((drv) + 2 * (chan)))
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#define SIS_CTRL1_PREFETCH_EN(chan, drv) (0x01 << ((drv) + 2 * (chan)))
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/* IDE misc control register (8 bit) */
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#define SIS_MISC 0x52
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#define SIS_MISC_TIM_SEL 0x08
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#define SIS_MISC_GTC 0x04
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#define SIS_MISC_FIFO_SIZE 0x01
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static int8_t sis_pio_act[] = {7, 5, 4, 3, 3};
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static int8_t sis_pio_rec[] = {7, 0, 5, 3, 1};
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#ifdef unused
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static int8_t sis_dma_act[] = {0, 3, 3};
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static int8_t sis_dma_rec[] = {0, 2, 1};
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#endif
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static int8_t sis_udma_tim[] = {3, 2, 1};
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