315 lines
13 KiB
C
315 lines
13 KiB
C
/* $NetBSD: if_sipreg.h,v 1.1 1999/06/01 18:19:13 thorpej Exp $ */
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/*-
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* Copyright (c) 1999 Network Computer, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Network Computer, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_IF_SIPREG_H_
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#define _DEV_PCI_IF_SIPREG_H_
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/*
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* Register description for the Silicon Integrated Systems SiS900
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* 10/100 PCI Ethernet controller.
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*
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* Written by Jason R. Thorpe for Network Computer, Inc.
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*/
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/*
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* Transmit FIFO size. Used to compute the transmit drain threshold.
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*
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* The transmit FIFO is arranged as a 512 32-bit memory array.
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*/
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#define SIP_TXFIFO_SIZE (512 * 4)
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/*
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* The SiS900 uses a single descriptor format for both transmit
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* and receive descriptor chains.
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*/
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struct sip_desc {
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u_int32_t sipd_link; /* link to next descriptor */
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u_int32_t sipd_cmdsts; /* command/status word */
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u_int32_t sipd_bufptr; /* pointer to DMA segment */
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};
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/*
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* CMDSTS bits common to transmit and receive.
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*/
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#define CMDSTS_OWN 0x80000000 /* owned by consumer */
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#define CMDSTS_MORE 0x40000000 /* more descriptors */
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#define CMDSTS_INTR 0x20000000 /* interrupt when ownership changes */
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#define CMDSTS_SUPCRC 0x10000000 /* suppress CRC */
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#define CMDSTS_OK 0x08000000 /* packet ok */
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#define CMDSTS_SIZE_MASK 0x000007ff /* packet size */
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#define CMDSTS_SIZE(x) ((x) & CMDSTS_SIZE_MASK)
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/*
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* CMDSTS bits for transmit.
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*/
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#define CMDSTS_Tx_TXA 0x04000000 /* transmit abort */
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#define CMDSTS_Tx_TFU 0x02000000 /* transmit FIFO underrun */
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#define CMDSTS_Tx_CRS 0x01000000 /* carrier sense lost */
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#define CMDSTS_Tx_TD 0x00800000 /* transmit deferred */
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#define CMDSTS_Tx_ED 0x00400000 /* excessive deferral */
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#define CMDSTS_Tx_OWC 0x00200000 /* out of window collision */
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#define CMDSTS_Tx_EC 0x00100000 /* excessive collisions */
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#define CMDSTS_Tx_CCNT 0x000f0000 /* collision count */
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#define CMDSTS_COLLISIONS(x) (((x) & CMDSTS_Tx_CCNT) >> 16)
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/*
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* CMDSTS bits for receive.
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*/
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#define CMDSTS_Rx_RXA 0x04000000 /* receive abort */
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#define CMDSTS_Rx_RXO 0x02000000 /* receive overrun */
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#define CMDSTS_Rx_DEST 0x01800000 /* destination class */
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#define CMDSTS_Rx_LONG 0x00400000 /* packet too long */
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#define CMDSTS_Rx_RUNT 0x00200000 /* runt packet */
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#define CMDSTS_Rx_ISE 0x00100000 /* invalid symbol error */
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#define CMDSTS_Rx_CRCE 0x00080000 /* CRC error */
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#define CMDSTS_Rx_FAE 0x00040000 /* frame alignment error */
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#define CMDSTS_Rx_LBP 0x00020000 /* loopback packet */
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#define CMDSTS_Rx_COL 0x00010000 /* collision activity */
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#define CMDSTS_Rx_DEST_REJ 0x00000000 /* packet rejected */
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#define CMDSTS_Rx_DEST_STA 0x00800000 /* matched station address */
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#define CMDSTS_Rx_DEST_MUL 0x01000000 /* multicast address */
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#define CMDSTS_Rx_DEST_BRD 0x01800000 /* broadcast address */
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/*
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* PCI Configuration space registers.
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*/
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#define SIP_PCI_CFGIOA (PCI_MAPREG_START + 0x00)
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#define SIP_PCI_CFGMA (PCI_MAPREG_START + 0x04)
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#define SIP_PCI_CFGEROMA 0x30 /* expansion ROM address */
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#define SIP_PCI_CFGPMC 0x40 /* power management cap. */
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#define SIP_PCI_CFGPMCSR 0x44 /* power management ctl. */
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/*
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* MAC Operation Registers
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*/
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#define SIP_CR 0x00 /* command register */
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#define CR_RST 0x00000100 /* software reset */
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#define CR_SWI 0x00000080 /* software interrupt */
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#define CR_RXR 0x00000020 /* receiver reset */
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#define CR_TXR 0x00000010 /* transmit reset */
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#define CR_RXD 0x00000008 /* receiver disable */
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#define CR_RXE 0x00000004 /* receiver enable */
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#define CR_TXD 0x00000002 /* transmit disable */
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#define CR_TXE 0x00000001 /* transmit enable */
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#define SIP_CFG 0x04 /* configuration register */
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#define CFG_REQALG 0x00000080 /* PCI bus request alg. */
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#define CFG_SB 0x00000040 /* single backoff */
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#define CFG_POW 0x00000020 /* program out of window timer */
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#define CFG_EXD 0x00000010 /* excessive defferal timer disable */
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#define CFG_PESEL 0x00000008 /* parity error detection action */
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#define CFG_BEM 0x00000001 /* big-endian mode */
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#define SIP_EROMAR 0x08 /* EEPROM access register */
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#define EROMAR_EECS 0x00000008 /* chip select */
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#define EROMAR_EESK 0x00000004 /* clock */
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#define EROMAR_EEDO 0x00000002 /* data out */
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#define EROMAR_EEDI 0x00000001 /* data in */
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#define SIP_PTSCR 0x0c /* PCI test control register */
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#define PTSCR_DIS_TEST 0x40000000 /* discard timer test mode */
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#define PTSCR_EROM_TACC 0x0f000000 /* boot rom access time */
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#define PTSCR_TRRAMADR 0x001ff000 /* TX/RX RAM address */
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#define PTSCR_BMTEN 0x00000200 /* bus master test enable */
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#define PTSCR_RRTMEN 0x00000080 /* receive RAM test mode enable */
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#define PTSCR_TRTMEN 0x00000040 /* transmit RAM test mode enable */
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#define PTSCR_SRTMEN 0x00000020 /* status RAM test mode enable */
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#define PTSCR_SRAMADR 0x0000001f /* status RAM address */
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#define SIP_ISR 0x10 /* interrupt status register */
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#define ISR_WAKEEVT 0x10000000 /* wake up event */
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#define ISR_PAUSE_END 0x08000000 /* end of transmission pause */
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#define ISR_PAUSE_ST 0x04000000 /* start of transmission pause */
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#define ISR_TXRCMP 0x02000000 /* transmit reset complete */
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#define ISR_RXRCMP 0x01000000 /* receive reset complete */
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#define ISR_DPERR 0x00800000 /* detected parity error */
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#define ISR_SSERR 0x00400000 /* signalled system error */
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#define ISR_RMABT 0x00200000 /* received master abort */
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#define ISR_RTABT 0x00100000 /* received target abort */
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#define ISR_RXSOVR 0x00010000 /* Rx status FIFO overrun */
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#define ISR_HIBERR 0x00008000 /* high bits error set */
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#define ISR_SWI 0x00001000 /* software interrupt */
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#define ISR_TXURN 0x00000400 /* Tx underrun */
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#define ISR_TXIDLE 0x00000200 /* Tx idle */
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#define ISR_TXERR 0x00000100 /* Tx error */
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#define ISR_TXDESC 0x00000080 /* Tx descriptor interrupt */
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#define ISR_TXOK 0x00000040 /* Tx okay */
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#define ISR_RXORN 0x00000020 /* Rx overrun */
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#define ISR_RXIDLE 0x00000010 /* Rx idle */
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#define ISR_RXEARLY 0x00000008 /* Rx early */
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#define ISR_RXERR 0x00000004 /* Rx error */
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#define ISR_RXDESC 0x00000002 /* Rx descriptor interrupt */
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#define ISR_RXOK 0x00000001 /* Rx okay */
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#define SIP_IMR 0x14 /* interrupt mask register */
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/* See bits in SIP_ISR */
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#define SIP_IER 0x18 /* interrupt enable register */
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#define IER_IE 0x00000001 /* master interrupt enable */
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#define SIP_ENPHY 0x1c /* enhanced PHY access register */
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#define ENPHY_PHYDATA 0xffff0000 /* PHY data */
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#define ENPHY_DATA_SHIFT 16
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#define ENPHY_REGADDR 0x000007c0 /* PHY register */
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#define ENPHY_REGADDR_SHIFT 6
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#define ENPHY_RWCMD 0x00000020 /* 1 == read, 0 == write */
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#define ENPHY_ACCESS 0x00000010 /* PHY access enable */
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#define SIP_TXDP 0x20 /* transmit descriptor pointer reg */
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#define SIP_TXCFG 0x24 /* transmit configuration register */
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#define TXCFG_CSI 0x80000000 /* carrier sense ignore */
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#define TXCFG_HBI 0x40000000 /* heartbeat ignore */
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#define TXCFG_MLB 0x20000000 /* MAC loopback */
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#define TXCFG_ATP 0x10000000 /* automatic transmit padding */
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#define TXCFG_MXDMA 0x00700000 /* max DMA burst size */
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#define TXCFG_MXDMA_512 0x00000000 /* 512 bytes */
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#define TXCFG_MXDMA_4 0x00100000 /* 4 bytes */
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#define TXCFG_MXDMA_8 0x00200000 /* 8 bytes */
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#define TXCFG_MXDMA_16 0x00300000 /* 16 bytes */
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#define TXCFG_MXDMA_32 0x00400000 /* 32 bytes */
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#define TXCFG_MXDMA_64 0x00500000 /* 64 bytes */
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#define TXCFG_MXDMA_128 0x00600000 /* 128 bytes */
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#define TXCFG_MXDMA_256 0x00700000 /* 256 bytes */
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#define TXCFG_FLTH 0x00003f00 /* Tx fill threshold */
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#define TXCFG_FLTH_SHIFT 8
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#define TXCFG_DRTH 0x0000003f /* Tx drain threshold */
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#define SIP_RXDP 0x30 /* receive desciptor pointer reg */
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#define SIP_RXCFG 0x34 /* receive configuration register */
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#define RXCFG_AEP 0x80000000 /* accept error packets */
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#define RXCFG_ARP 0x40000000 /* accept runt packets */
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#define RXCFG_ATX 0x10000000 /* accept transmit packets */
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#define RXCFG_AJAB 0x08000000 /* accept jabber packets */
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#define RXCFG_MXDMA 0x00700000 /* max DMA burst size */
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#define RXCFG_MXDMA_512 0x00000000 /* 512 bytes */
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#define RXCFG_MXDMA_4 0x00100000 /* 4 bytes */
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#define RXCFG_MXDMA_8 0x00200000 /* 8 bytes */
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#define RXCFG_MXDMA_16 0x00300000 /* 16 bytes */
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#define RXCFG_MXDMA_32 0x00400000 /* 32 bytes */
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#define RXCFG_MXDMA_64 0x00500000 /* 64 bytes */
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#define RXCFG_MXDMA_128 0x00600000 /* 128 bytes */
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#define RXCFG_MXDMA_256 0x00700000 /* 256 bytes */
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#define RXCFG_DRTH 0x0000003e
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#define RXCFG_DRTH_SHIFT 1
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#define SIP_FLOWCTL 0x38 /* flow control register */
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#define FLOWCTL_PAUSE 0x00000002 /* PAUSE flag */
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#define FLOWCTL_FLOWEN 0x00000001 /* enable flow control */
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#define SIP_RFCR 0x48 /* receive filter control register */
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#define RFCR_RFEN 0x80000000 /* Rx filter enable */
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#define RFCR_AAB 0x40000000 /* accept all broadcast */
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#define RFCR_AAM 0x20000000 /* accept all multicast */
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#define RFCR_AAP 0x10000000 /* accept all physical */
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#define RFCR_RFADDR 0x000f0000 /* Rx filter address */
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#define RFCR_RFADDR_NODE0 0x00000000 /* node address 1, 0 */
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#define RFCR_RFADDR_NODE2 0x00010000 /* node address 3, 2 */
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#define RFCR_RFADDR_NODE4 0x00020000 /* node address 5, 4 */
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#define RFCR_RFADDR_MC0 0x00040000 /* multicast hash word 0 */
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#define RFCR_RFADDR_MC1 0x00050000 /* multicast hash word 1 */
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#define RFCR_RFADDR_MC2 0x00060000 /* multicast hash word 2 */
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#define RFCR_RFADDR_MC3 0x00070000 /* multicast hash word 3 */
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#define RFCR_RFADDR_MC4 0x00080000 /* multicast hash word 4 */
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#define RFCR_RFADDR_MC5 0x00090000 /* multicast hash word 5 */
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#define RFCR_RFADDR_MC6 0x000a0000 /* multicast hash word 6 */
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#define RFCR_RFADDR_MC7 0x000b0000 /* multicast hash word 7 */
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#define SIP_RFDR 0x4c /* receive filter data register */
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#define RFDR_DATA 0x0000ffff /* data bits */
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#define SIP_PMCTL 0xb0 /* power management control register */
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#define PMCTL_GATECLK 0x80000000 /* gate dual clock enable */
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#define PMCTL_WAKEALL 0x40000000 /* wake on all Rx OK */
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#define PMCTL_FRM3ACS 0x04000000 /* 3rd wake-up frame access */
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#define PMCTL_FRM2ACS 0x02000000 /* 2nd wake-up frame access */
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#define PMCTL_FRM1ACS 0x01000000 /* 1st wake-up frame access */
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#define PMCTL_FRM3EN 0x00400000 /* 3rd wake-up frame match enable */
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#define PMCTL_FRM2EN 0x00200000 /* 2nd wake-up frame match enable */
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#define PMCTL_FRM1EN 0x00100000 /* 1st wake-up frame match enable */
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#define PMCTL_ALGORITHM 0x00000800 /* Magic Packet match algorithm */
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#define PMCTL_MAGICPKT 0x00000400 /* Magic Packet match enable */
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#define PMCTL_LINKON 0x00000002 /* link on monitor enable */
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#define PMCTL_LINKLOSS 0x00000001 /* link loss monitor enable */
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#define SIP_PMEVT 0xb4 /* power management wake-up evnt reg */
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#define PMEVT_ALLFRMMAT 0x40000000 /* receive packet ok */
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#define PMEVT_FRM3MAT 0x04000000 /* match 3rd wake-up frame */
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#define PMEVT_FRM2MAT 0x02000000 /* match 2nd wake-up frame */
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#define PMEVT_FRM1MAT 0x01000000 /* match 1st wake-up frame */
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#define PMEVT_MAGICPKT 0x00000400 /* Magic Packet */
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#define PMEVT_ONEVT 0x00000002 /* link on event */
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#define PMEVT_LOSSEVT 0x00000001 /* link loss event */
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#define SIP_WAKECRC 0xbc /* wake-up frame CRC register */
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#define SIP_WAKEMASK0 0xc0 /* wake-up frame mask registers */
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#define SIP_WAKEMASK1 0xc4
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#define SIP_WAKEMASK2 0xc8
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#define SIP_WAKEMASK3 0xcc
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#define SIP_WAKEMASK4 0xe0
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#define SIP_WASKMASK5 0xe4
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#define SIP_WAKEMASK6 0xe8
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#define SIP_WAKEMASK7 0xec
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/*
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* Serial EEPROM opcodes, including the start bit.
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*/
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#define SIP_EEPROM_OPC_ERASE 0x04
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#define SIP_EEPROM_OPC_WRITE 0x05
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#define SIP_EEPROM_OPC_READ 0x06
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/*
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* Serial EEPROM address map (byte address).
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*/
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#define SIP_EEPROM_SIGNATURE 0x00 /* SiS 900 signature */
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#define SIP_EEPROM_MASK 0x02 /* `enable' mask */
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#define SIP_EEPROM_VENDOR_ID 0x04 /* PCI vendor ID */
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#define SIP_EEPROM_DEVICE_ID 0x06 /* PCI device ID */
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#define SIP_EEPROM_SUBVENDOR_ID 0x08 /* PCI subvendor ID */
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#define SIP_EEPROM_SUBSYSTEM_ID 0x0a /* PCI subsystem ID */
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#define SIP_EEPROM_PMC 0x0c /* PCI power management capabilities */
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#define SIP_EEPROM_reserved 0x0e /* reserved */
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#define SIP_EEPROM_ETHERNET_ID0 0x10 /* Ethernet address 0, 1 */
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#define SIP_EEPROM_ETHERNET_ID1 0x12 /* Ethernet address 2, 3 */
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#define SIP_EEPROM_ETHERNET_ID2 0x14 /* Ethernet address 4, 5 */
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#define SIP_EEPROM_CHECKSUM 0x16 /* checksum */
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#endif /* _DEV_PCI_IF_SIPREG_H_ */
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