269 lines
10 KiB
C
269 lines
10 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Tim L. Tucker.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)if_wereg.h 7.1 (Berkeley) 5/9/91
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*/
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/*
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* Western Digital 8003 ethernet/starlan adapter
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*/
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/*
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* Memory Select Register (MSR)
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*/
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union we_mem_sel {
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struct memory_decode {
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u_char msd_addr:6, /* Memory decode bits */
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msd_enable:1, /* Memory (RAM) enable */
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msd_reset:1; /* Software reset */
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} msd_decode;
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#define ms_addr msd_decode.msd_addr
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#define ms_enable msd_decode.msd_enable
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#define ms_reset msd_decode.msd_reset
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u_char ms_byte; /* entire byte */
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};
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/*
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* LA Address Register (LAAR)
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*/
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union we_laar {
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struct lan_addr_reg {
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u_char addr_l19_b:1, /* Address Line 19 for enabling */
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/* 16 bit NIC access to shared RAM */
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unused_b:5, /* unused (or unknown) bits */
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lan_16_en_b:1, /* Enables 16bit shrd RAM for LAN */
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mem_16_en_b:1; /* Enables 16bit shrd RAM for host */
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} laar_decode;
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#define addr_l19 laar_decode.addr_l19_b
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#define lan_16_en laar_decode.lan_16_en_b
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#define mem_16_en laar_decode.mem_16_en_b
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u_char laar_byte; /* entire byte */
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};
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/*
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* receive ring discriptor
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*
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* The National Semiconductor DS8390 Network interface controller uses
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* the following receive ring headers. The way this works is that the
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* memory on the interface card is chopped up into 256 bytes blocks.
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* A contiguous portion of those blocks are marked for receive packets
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* by setting start and end block #'s in the NIC. For each packet that
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* is put into the receive ring, one of these headers (4 bytes each) is
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* tacked onto the front.
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*/
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struct we_ring {
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struct wer_status { /* received packet status */
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u_char rs_prx:1, /* packet received intack */
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rs_crc:1, /* crc error */
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rs_fae:1, /* frame alignment error */
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rs_fo:1, /* fifo overrun */
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rs_mpa:1, /* packet received intack */
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rs_phy:1, /* packet received intack */
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rs_dis:1, /* packet received intack */
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rs_dfr:1; /* packet received intack */
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} we_rcv_status; /* received packet status */
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u_char we_next_packet; /* pointer to next packet */
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u_short we_count; /* bytes in packet (length + 4) */
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};
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/*
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* Command word definition
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*/
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union we_command {
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struct command_decode {
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u_char csd_stp:1, /* STOP! */
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csd_sta:1, /* START! */
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csd_txp:1, /* Transmit packet */
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csd_rd:3, /* Remote DMA command */
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csd_ps:2; /* Page select */
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} csd_decode;
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#define cs_stp csd_decode.csd_stp
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#define cs_sta csd_decode.csd_sta
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#define cs_txp csd_decode.csd_txp
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#define cs_rd csd_decode.csd_rd
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#define cs_ps csd_decode.csd_ps
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u_char cs_byte; /* entire command byte */
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};
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/*
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* Interrupt status definition
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*/
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union we_interrupt {
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struct interrupt_decode {
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u_char isd_prx:1, /* Packet received */
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isd_ptx:1, /* Packet transmitted */
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isd_rxe:1, /* Receive error */
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isd_txe:1, /* Transmit error */
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isd_ovw:1, /* Overwrite warning */
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isd_cnt:1, /* Counter overflow */
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isd_rdc:1, /* Remote DMA complete */
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isd_rst:1; /* Reset status */
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} isd_decode;
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#define is_prx isd_decode.isd_prx
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#define is_ptx isd_decode.isd_ptx
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#define is_rxe isd_decode.isd_rxe
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#define is_txe isd_decode.isd_txe
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#define is_ovw isd_decode.isd_ovw
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#define is_cnt isd_decode.isd_cnt
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#define is_rdc isd_decode.isd_rdc
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#define is_rst isd_decode.isd_rst
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u_char is_byte; /* entire interrupt byte */
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};
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/*
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* Status word definition (transmit)
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*/
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union wet_status {
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struct tstat {
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u_char tsd_ptx:1, /* Packet transmitted intack */
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tsd_dfr:1, /* Non deferred transmition */
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tsd_col:1, /* Transmit Collided */
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tsd_abt:1, /* Transmit Aborted (coll > 16) */
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tsd_crs:1, /* Carrier Sense Lost */
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tsd_fu:1, /* Fifo Underrun */
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tsd_chd:1, /* CD Heartbeat */
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tsd_owc:1; /* Out of Window Collision */
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} tsd_decode;
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#define ts_ptx tsd_decode.tsd_ptx
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#define ts_dfr tsd_decode.tsd_dfr
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#define ts_col tsd_decode.tsd_col
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#define ts_abt tsd_decode.tsd_abt
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#define ts_crs tsd_decode.tsd_crs
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#define ts_fu tsd_decode.tsd_fu
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#define ts_chd tsd_decode.tsd_chd
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#define ts_owc tsd_decode.tsd_owc
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u_char ts_byte; /* entire transmit byte */
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};
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/*
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* General constant definitions
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*/
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/* Bits in the REGE register */
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#define WD_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
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#define WD_LARGERAM 0x40 /* Large RAM */
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#define WD_SOFTCONFIG 0x20 /* Soft config */
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#define WD_REVMASK 0x1e /* Revision mask */
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#define WD_ETHERNET 0x01 /* Ethernet (vs. Starlan) */
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#define WD_CHECKSUM 0xFF /* Checksum byte */
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#define WD_PAGE_SIZE 256 /* Size of RAM pages in bytes */
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#define WD_TXBUF_SIZE 6 /* Size of TX buffer in pages */
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#define WD_ROM_OFFSET 8 /* i/o base offset to ROM */
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#define WD_IO_PORTS 32 /* # of i/o addresses used */
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#define WD_NIC_OFFSET 16 /* i/o base offset to NIC */
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/*
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* Page register offset values
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*/
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#define WD_P0_COMMAND 0x00 /* Command register */
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#define WD_P0_PSTART 0x01 /* Page Start register */
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#define WD_P0_PSTOP 0x02 /* Page Stop register */
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#define WD_P0_BNRY 0x03 /* Boundary Pointer */
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#define WD_P0_TSR 0x04 /* Transmit Status (read-only) */
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#define WD_P0_TPSR WD_P0_TSR /* Transmit Page (write-only) */
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#define WD_P0_TBCR0 0x05 /* Transmit Byte count, low WO */
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#define WD_P0_TBCR1 0x06 /* Transmit Byte count, high WO */
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#define WD_P0_ISR 0x07 /* Interrupt status register */
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#define WD_P0_RBCR0 0x0A /* Remote byte count low WO */
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#define WD_P0_RBCR1 0x0B /* Remote byte count high WO */
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#define WD_P0_RSR 0x0C /* Receive status RO */
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#define WD_P0_RCR WD_P0_RSR /* Receive configuration WO */
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#define WD_P0_TCR 0x0D /* Transmit configuration WO */
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#define WD_P0_DCR 0x0E /* Data configuration WO */
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#define WD_P0_IMR 0x0F /* Interrupt masks WO */
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#define WD_P1_COMMAND 0x00 /* Command register */
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#define WD_P1_PAR0 0x01 /* Physical address register 0 */
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#define WD_P1_PAR1 0x02 /* Physical address register 1 */
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#define WD_P1_PAR2 0x03 /* Physical address register 2 */
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#define WD_P1_PAR3 0x04 /* Physical address register 3 */
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#define WD_P1_PAR4 0x05 /* Physical address register 4 */
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#define WD_P1_PAR5 0x06 /* Physical address register 5 */
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#define WD_P1_CURR 0x07 /* Current page (receive unit) */
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#define WD_P1_MAR0 0x08 /* Multicast address register 0 */
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/*
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* Configuration constants (receive unit)
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*/
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#define WD_R_SEP 0x01 /* Save error packets */
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#define WD_R_AR 0x02 /* Accept Runt packets */
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#define WD_R_AB 0x04 /* Accept Broadcast packets */
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#define WD_R_AM 0x08 /* Accept Multicast packets */
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#define WD_R_PRO 0x10 /* Promiscuous physical */
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#define WD_R_MON 0x20 /* Monitor mode */
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#define WD_R_RES1 0x40 /* reserved... */
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#define WD_R_RES2 0x80 /* reserved... */
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#define WD_R_CONFIG (WD_R_AB)
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/*
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* Configuration constants (transmit unit)
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*/
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#define WD_T_CRC 0x01 /* Inhibit CRC */
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#define WD_T_LB0 0x02 /* Encoded Loopback Control */
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#define WD_T_LB1 0x04 /* Encoded Loopback Control */
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#define WD_T_ATD 0x08 /* Auto Transmit Disable */
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#define WD_T_OFST 0x10 /* Collision Offset Enable */
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#define WD_T_RES1 0x20 /* reserved... */
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#define WD_T_RES2 0x40 /* reserved... */
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#define WD_T_RES3 0x80 /* reserved... */
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#define WD_T_CONFIG (0)
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/*
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* Configuration constants (data unit)
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*/
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#define WD_D_WTS 0x01 /* Word Transfer Select */
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#define WD_D_BOS 0x02 /* Byte Order Select */
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#define WD_D_LAS 0x04 /* Long Address Select */
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#define WD_D_BMS 0x08 /* Burst Mode Select */
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#define WD_D_AR 0x10 /* Autoinitialize Remote */
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#define WD_D_FT0 0x20 /* Fifo Threshold Select */
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#define WD_D_FT1 0x40 /* Fifo Threshold Select */
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#define WD_D_RES 0x80 /* reserved... */
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#define WD_D_CONFIG (WD_D_FT1|WD_D_BMS)
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#define WD_D_CONFIG16 (WD_D_FT1|WD_D_BMS|WD_D_LAS|WD_D_WTS)
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/*
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* Configuration constants (interrupt mask register)
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*/
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#define WD_I_PRXE 0x01 /* Packet received enable */
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#define WD_I_PTXE 0x02 /* Packet transmitted enable */
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#define WD_I_RXEE 0x04 /* Receive error enable */
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#define WD_I_TXEE 0x08 /* Transmit error enable */
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#define WD_I_OVWE 0x10 /* Overwrite warning enable */
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#define WD_I_CNTE 0x20 /* Counter overflow enable */
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#define WD_I_RDCE 0x40 /* Dma complete enable */
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#define WD_I_RES 0x80 /* reserved... */
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#define WD_I_CONFIG (WD_I_PRXE|WD_I_PTXE|WD_I_RXEE|WD_I_TXEE)
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