58 lines
2.3 KiB
C
58 lines
2.3 KiB
C
/* $NetBSD: ifpga_pcivar.h,v 1.1 2001/10/27 16:19:09 rearnsha Exp $ */
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/*
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* Copyright (c) 2001 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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struct ifpga_pci_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_io_ioh;
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bus_space_handle_t sc_conf_ioh;
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_app0_ioh;
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bus_space_handle_t sc_app1_ioh;
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bus_space_handle_t sc_reg_ioh;
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};
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/* Apperture 0, 256MB normal cycles. */
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#define IFPGA_PCI_APP0_256MB_BASE 0x40000081
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#define IFPGA_PCI_APP0_512MB_BASE 0x40000091
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#define IFPGA_PCI_APP0_256MB_MAP 0x4006
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/* Apperture 1, 256MB normal cycles, prefetchable. */
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#define IFPGA_PCI_APP1_256MB_BASE 0x50000081
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#define IFPGA_PCI_APP1_256MB_MAP 0x5006
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/* Apperture 1, 16MB configuration cycles. */
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#define IFPGA_PCI_APP1_CONF_BASE 0x61000041
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#define IFPGA_PCI_APP1_CONF_T0_MAP 0x000a /* Type 0 cycle */
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#define IFPGA_PCI_APP1_CONF_T1_MAP 0x000b /* Type 1 cycle */
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