247 lines
6.1 KiB
C
247 lines
6.1 KiB
C
/* $NetBSD: g2bus_bus_mem.c,v 1.3 2001/02/01 01:01:50 thorpej Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Bus space implementation for the SEGA G2 bus.
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*
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* NOTE: We only implement a small subset of what the bus_space(9)
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* API specifies. Right now, the GAPS PCI bridge is only used for
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* the Dreamcast Broadband Adatper, so we only provide what the
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* pci(4) and rtk(4) drivers need.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/cpufunc.h>
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#include <dreamcast/dev/g2/g2busvar.h>
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int g2bus_bus_mem_map(void *, bus_addr_t, bus_size_t, int,
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bus_space_handle_t *);
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void g2bus_bus_mem_unmap(void *, bus_space_handle_t, bus_size_t);
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u_int8_t g2bus_bus_mem_read_1(void *, bus_space_handle_t, bus_size_t);
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u_int16_t g2bus_bus_mem_read_2(void *, bus_space_handle_t, bus_size_t);
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u_int32_t g2bus_bus_mem_read_4(void *, bus_space_handle_t, bus_size_t);
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void g2bus_bus_mem_write_1(void *, bus_space_handle_t, bus_size_t,
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u_int8_t);
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void g2bus_bus_mem_write_2(void *, bus_space_handle_t, bus_size_t,
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u_int16_t);
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void g2bus_bus_mem_write_4(void *, bus_space_handle_t, bus_size_t,
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u_int32_t);
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void g2bus_bus_mem_read_region_1(void *, bus_space_handle_t, bus_size_t,
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u_int8_t *, bus_size_t);
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void g2bus_bus_mem_write_region_1(void *, bus_space_handle_t, bus_size_t,
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const u_int8_t *, bus_size_t);
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void
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g2bus_bus_mem_init(struct g2bus_softc *sc)
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{
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bus_space_tag_t t = &sc->sc_memt;
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memset(t, 0, sizeof(*t));
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t->dbs_map = g2bus_bus_mem_map;
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t->dbs_unmap = g2bus_bus_mem_unmap;
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t->dbs_r_1 = g2bus_bus_mem_read_1;
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t->dbs_r_2 = g2bus_bus_mem_read_2;
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t->dbs_r_4 = g2bus_bus_mem_read_4;
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t->dbs_w_1 = g2bus_bus_mem_write_1;
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t->dbs_w_2 = g2bus_bus_mem_write_2;
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t->dbs_w_4 = g2bus_bus_mem_write_4;
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t->dbs_rr_1 = g2bus_bus_mem_read_region_1;
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t->dbs_wr_1 = g2bus_bus_mem_write_region_1;
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}
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int
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g2bus_bus_mem_map(void *v, bus_addr_t addr, bus_size_t size, int flags,
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bus_space_handle_t *shp)
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{
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KASSERT((addr & SH3_PHYS_MASK) == addr);
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*shp = SH3_PHYS_TO_P2SEG(addr);
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return (0);
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}
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void
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g2bus_bus_mem_unmap(void *v, bus_space_handle_t sh, bus_size_t size)
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{
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KASSERT(sh >= SH3_P2SEG_BASE && sh <= SH3_P2SEG_END);
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/* Nothing to do. */
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}
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/*
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* G2 bus cycles must not be interrupted by IRQs or G2 DMA.
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* The following paired macros will take the necessary precautions.
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*/
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#define G2_LOCK \
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do { \
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disable_intr(); \
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/* suspend any G2 DMA here... */ \
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while((*(volatile unsigned int *)0xa05f688c) & 32); \
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} while(0)
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#define G2_UNLOCK \
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do { \
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/* resume any G2 DMA here... */ \
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enable_intr(); \
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} while(0)
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u_int8_t
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g2bus_bus_mem_read_1(void *v, bus_space_handle_t sh, bus_size_t off)
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{
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u_int8_t rv;
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G2_LOCK;
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rv = *(__volatile u_int8_t *)(sh + off);
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G2_UNLOCK;
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return (rv);
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}
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u_int16_t
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g2bus_bus_mem_read_2(void *v, bus_space_handle_t sh, bus_size_t off)
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{
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u_int16_t rv;
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G2_LOCK;
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rv = *(__volatile u_int16_t *)(sh + off);
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G2_UNLOCK;
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return (rv);
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}
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u_int32_t
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g2bus_bus_mem_read_4(void *v, bus_space_handle_t sh, bus_size_t off)
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{
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u_int32_t rv;
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G2_LOCK;
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rv = *(__volatile u_int32_t *)(sh + off);
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G2_UNLOCK;
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return (rv);
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}
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void
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g2bus_bus_mem_write_1(void *v, bus_space_handle_t sh, bus_size_t off,
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u_int8_t val)
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{
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G2_LOCK;
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*(__volatile u_int8_t *)(sh + off) = val;
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G2_UNLOCK;
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}
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void
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g2bus_bus_mem_write_2(void *v, bus_space_handle_t sh, bus_size_t off,
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u_int16_t val)
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{
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G2_LOCK;
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*(__volatile u_int16_t *)(sh + off) = val;
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G2_UNLOCK;
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}
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void
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g2bus_bus_mem_write_4(void *v, bus_space_handle_t sh, bus_size_t off,
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u_int32_t val)
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{
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G2_LOCK;
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*(__volatile u_int32_t *)(sh + off) = val;
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G2_UNLOCK;
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}
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void
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g2bus_bus_mem_read_region_1(void *v, bus_space_handle_t sh, bus_size_t off,
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u_int8_t *addr, bus_size_t len)
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{
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__volatile const u_int8_t *baddr = (u_int8_t *)(sh + off);
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G2_LOCK;
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while (len--)
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*addr++ = *baddr++;
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G2_UNLOCK;
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}
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void
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g2bus_bus_mem_write_region_1(void *v, bus_space_handle_t sh, bus_size_t off,
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const u_int8_t *addr, bus_size_t len)
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{
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__volatile u_int8_t *baddr = (u_int8_t *)(sh + off);
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G2_LOCK;
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while (len--)
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*baddr++ = *addr++;
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G2_UNLOCK;
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}
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