131 lines
4.7 KiB
C
131 lines
4.7 KiB
C
/* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */
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/*
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* Copyright (c) 1994 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the RiscBSD team.
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* 4. The name "RiscBSD" nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM32_PTE_H_
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#define _ARM32_PTE_H_
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#define PDSHIFT 20 /* LOG2(NBPDR) */
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#define NBPD (1 << PDSHIFT) /* bytes/page dir */
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#define NPTEPD (NBPD / NBPG)
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#ifndef _LOCORE
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typedef int pd_entry_t; /* page directory entry */
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typedef int pt_entry_t; /* page table entry */
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#endif
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#define PD_MASK 0xfff00000 /* page directory address bits */
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#define PT_MASK 0x000ff000 /* page table address bits */
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#define PG_FRAME 0xfffff000
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/* The PT_SIZE definition is misleading... A page table is only 0x400
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* bytes long. But since VM mapping can only be done to 0x1000 a single
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* 1KB blocks cannot be steered to a va by itself. Therefore the
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* pages tables are allocated in blocks of 4. i.e. if a 1 KB block
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* was allocated for a PT then the other 3KB would also get mapped
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* whenever the 1KB was mapped.
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*/
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#define PT_SIZE 0x1000
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#define PD_SIZE 0x4000
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/* Access permissions for L1 sections and L2 pages */
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#define AP_KR 0x00
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#define AP_KRW 0x01
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#define AP_KRWUR 0x02
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#define AP_KRWURW 0x03
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#define AP_W 0x01
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#define AP_U 0x02
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/* Physical bits in a pte */
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#define PT_B 0x04 /* Phys - Buffered (write) */
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#define PT_C 0x08 /* Phys - Cacheable */
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#define PT_U 0x10 /* Phys - Updateable */
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#ifndef _LOCORE
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extern pt_entry_t pte_cache_mode;
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#define PT_CACHEABLE (pte_cache_mode)
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#endif
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/* Page R/M attributes (in pmseg.attrs). */
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#define PT_M 0x01 /* Virt - Modified */
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#define PT_H 0x02 /* Virt - Handled (Used) */
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/* Mapping wired/writeable/cacheable attributes (in pv_flags). */
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#define PT_W 0x04 /* Virt - Wired */
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#define PT_Wr 0x08 /* Virt / Phys Write */
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#define PT_NC 0x10 /* Cacheing disabled (multi-mapped page) */
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/* access permissions for L2 pages (all sub pages have the same perms) */
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#define PT_AP(x) ((x << 10) | (x << 8) | (x << 6) | (x << 4))
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/* shift for access permissions in a L1 section mapping */
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#define AP_SECTION_SHIFT 10
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/* Page table types and masks */
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#define L1_PAGE 0x01 /* L1 page table mapping */
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#define L1_SECTION 0x02 /* L1 section mapping */
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#define L1_FPAGE 0x03 /* L1 fine page mapping */
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#define L1_MASK 0x03 /* Mask for L1 entry type */
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#define L2_LPAGE 0x01 /* L2 large page (64KB) */
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#define L2_SPAGE 0x02 /* L2 small page (4KB) */
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#define L2_MASK 0x03 /* Mask for L2 entry type */
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#define L2_INVAL 0x00 /* L2 invalid type */
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/* PTE construction macros */
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#define L2_LPTE(p, a, f) ((p) | PT_AP(a) | L2_LPAGE | (f))
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#define L2_SPTE(p, a, f) ((p) | PT_AP(a) | L2_SPAGE | (f))
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#define L2_PTE(p, a) L2_SPTE((p), (a), PT_CACHEABLE)
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#define L2_PTE_NC(p, a) L2_SPTE((p), (a), PT_B)
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#define L2_PTE_NC_NB(p, a) L2_SPTE((p), (a), 0)
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#define L1_SECPTE(p, a, f) ((p) | ((a) << AP_SECTION_SHIFT) | (f) \
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| L1_SECTION | PT_U)
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#define L1_PTE(p) ((p) | 0x00 | L1_PAGE | PT_U)
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#define L1_SEC(p, c) L1_SECPTE((p), AP_KRW, (c))
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#define L1_SEC_SIZE (1 << PDSHIFT)
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#define L2_LPAGE_SIZE (NBPG * 16)
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/* Domain types */
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#define DOMAIN_FAULT 0x00
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#define DOMAIN_CLIENT 0x01
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#define DOMAIN_RESERVED 0x02
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#define DOMAIN_MANAGER 0x03
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#endif
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/* End of pte.h */
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