9b4c0e34d2
x86-64. Since there's no hardware available yet, this port is only known to run on the Simics simulator for at the moment, and as such uses the PC devices that it simulates for now. It will be developed more (and cleaned up) as the hardware becomes available.
274 lines
7.7 KiB
C
274 lines
7.7 KiB
C
/* $NetBSD: pchb.c,v 1.1 2001/06/19 00:20:45 fvdl Exp $ */
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/*-
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* Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <arch/i386/pci/pchbvar.h>
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#include "rnd.h"
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#define PCISET_BRIDGETYPE_MASK 0x3
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#define PCISET_TYPE_COMPAT 0x1
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#define PCISET_TYPE_AUX 0x2
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#define PCISET_BUSCONFIG_REG 0x48
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#define PCISET_BRIDGE_NUMBER(reg) (((reg) >> 8) & 0xff)
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#define PCISET_PCI_BUS_NUMBER(reg) (((reg) >> 16) & 0xff)
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/* XXX should be in dev/ic/i82443reg.h */
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#define I82443BX_SDRAMC_REG 0x76
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/* XXX should be in dev/ic/i82424{reg.var}.h */
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#define I82424_CPU_BCTL_REG 0x53
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#define I82424_PCI_BCTL_REG 0x54
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#define I82424_BCTL_CPUMEM_POSTEN 0x01
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#define I82424_BCTL_CPUPCI_POSTEN 0x02
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#define I82424_BCTL_PCIMEM_BURSTEN 0x01
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#define I82424_BCTL_PCI_BURSTEN 0x02
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int pchbmatch __P((struct device *, struct cfdata *, void *));
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void pchbattach __P((struct device *, struct device *, void *));
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int pchb_print __P((void *, const char *));
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struct cfattach pchb_ca = {
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sizeof(struct pchb_softc), pchbmatch, pchbattach
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};
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int
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pchbmatch(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct pci_attach_args *pa = aux;
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) {
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return (1);
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}
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return (0);
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}
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void
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pchbattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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#if NRND > 0
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struct pchb_softc *sc = (void *) self;
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#endif
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struct pci_attach_args *pa = aux;
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char devinfo[256];
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struct pcibus_attach_args pba;
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pcireg_t bcreg;
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u_char bdnum, pbnum;
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pcitag_t tag;
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int doattach;
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printf("\n");
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doattach = 0;
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/*
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* Print out a description, and configure certain chipsets which
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* have auxiliary PCI buses.
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*/
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pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
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printf("%s: %s (rev. 0x%02x)\n", self->dv_xname, devinfo,
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PCI_REVISION(pa->pa_class));
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switch (PCI_VENDOR(pa->pa_id)) {
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case PCI_VENDOR_SERVERWORKS:
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pbnum = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x44) & 0xff;
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if (pbnum == 0)
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break;
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/*
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* This host bridge has a second PCI bus.
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* Configure it.
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*/
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doattach = 1;
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break;
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case PCI_VENDOR_INTEL:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_INTEL_82443BX_AGP:
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case PCI_PRODUCT_INTEL_82443BX_NOAGP:
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/*
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* BIOS BUG WORKAROUND! The 82443BX
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* datasheet indicates that the only
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* legal setting for the "Idle/Pipeline
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* DRAM Leadoff Timing (IPLDT)" parameter
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* (bits 9:8) is 01. Unfortunately, some
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* BIOSs do not set these bits properly.
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*/
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bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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I82443BX_SDRAMC_REG);
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if ((bcreg & 0x0300) != 0x0100) {
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printf("%s: fixing Idle/Pipeline DRAM "
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"Leadoff Timing\n", self->dv_xname);
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bcreg &= ~0x0300;
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bcreg |= 0x0100;
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pci_conf_write(pa->pa_pc, pa->pa_tag,
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I82443BX_SDRAMC_REG, bcreg);
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}
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break;
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case PCI_PRODUCT_INTEL_PCI450_PB:
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bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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PCISET_BUSCONFIG_REG);
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bdnum = PCISET_BRIDGE_NUMBER(bcreg);
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pbnum = PCISET_PCI_BUS_NUMBER(bcreg);
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switch (bdnum & PCISET_BRIDGETYPE_MASK) {
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default:
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printf("%s: bdnum=%x (reserved)\n",
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self->dv_xname, bdnum);
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break;
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case PCISET_TYPE_COMPAT:
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printf("%s: Compatibility PB (bus %d)\n",
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self->dv_xname, pbnum);
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break;
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case PCISET_TYPE_AUX:
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printf("%s: Auxiliary PB (bus %d)\n",
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self->dv_xname, pbnum);
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/*
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* This host bridge has a second PCI bus.
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* Configure it.
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*/
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doattach = 1;
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break;
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}
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break;
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case PCI_PRODUCT_INTEL_CDC:
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bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
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I82424_CPU_BCTL_REG);
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if (bcreg & I82424_BCTL_CPUPCI_POSTEN) {
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bcreg &= ~I82424_BCTL_CPUPCI_POSTEN;
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pci_conf_write(pa->pa_pc, pa->pa_tag,
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I82424_CPU_BCTL_REG, bcreg);
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printf("%s: disabled CPU-PCI write posting\n",
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self->dv_xname);
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}
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break;
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case PCI_PRODUCT_INTEL_82451NX_PXB:
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/*
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* The NX chipset supports up to 2 "PXB" chips
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* which can drive 2 PCI buses each. Each bus
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* shows up as logical PCI device, with fixed
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* device numbers between 18 and 21.
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* See the datasheet at
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ftp://download.intel.com/design/chipsets/datashts/24377102.pdf
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* for details.
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* (It would be easier to attach all the buses
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* at the MIOC, but less aesthetical imho.)
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*/
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pbnum = 0;
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switch (pa->pa_device) {
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case 18: /* PXB 0 bus A - primary bus */
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break;
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case 19: /* PXB 0 bus B */
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/* read SUBA0 from MIOC */
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tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
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bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
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pbnum = ((bcreg & 0x0000ff00) >> 8) + 1;
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break;
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case 20: /* PXB 1 bus A */
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/* read BUSNO1 from MIOC */
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tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
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bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
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pbnum = (bcreg & 0xff000000) >> 24;
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break;
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case 21: /* PXB 1 bus B */
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/* read SUBA1 from MIOC */
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tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
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bcreg = pci_conf_read(pa->pa_pc, tag, 0xd4);
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pbnum = (bcreg & 0x000000ff) + 1;
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break;
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}
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if (pbnum != 0)
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doattach = 1;
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break;
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}
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break;
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}
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if (doattach) {
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pba.pba_busname = "pci";
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pba.pba_iot = pa->pa_iot;
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pba.pba_memt = pa->pa_memt;
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pba.pba_dmat = pa->pa_dmat;
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pba.pba_bus = pbnum;
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pba.pba_flags = pa->pa_flags;
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pba.pba_pc = pa->pa_pc;
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config_found(self, &pba, pchb_print);
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}
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#if NRND > 0
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/*
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* Attach a random number generator, if there is one.
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*/
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pchb_attach_rnd(sc, pa);
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#endif
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}
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int
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pchb_print(aux, pnp)
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void *aux;
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const char *pnp;
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{
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struct pcibus_attach_args *pba = aux;
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if (pnp)
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printf("%s at %s", pba->pba_busname, pnp);
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printf(" bus %d", pba->pba_bus);
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return (UNCONF);
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}
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