136 lines
5.0 KiB
C
136 lines
5.0 KiB
C
/* $NetBSD: fsr.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)fsr.h 8.1 (Berkeley) 6/11/93
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*/
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#ifndef _MACHINE_FSR_H_
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#define _MACHINE_FSR_H_
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/*
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* Bits in FPRS
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*/
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#define FPRS_FEF 0x04 /* Enable FP -- must be set to enable FP regs */
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#define FPRS_DU 0x02 /* Dirty upper -- upper fp regs are dirty */
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#define FPRS_DL 0x01 /* Dirty lower -- lower fp regs are dirty */
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/*
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* Bits in FSR.
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*/
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#define FSR_RD 0xc0000000 /* rounding direction */
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#define FSR_RD_RN 0 /* round to nearest */
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#define FSR_RD_RZ 1 /* round towards 0 */
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#define FSR_RD_RP 2 /* round towards +inf */
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#define FSR_RD_RM 3 /* round towards -inf */
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#define FSR_RD_SHIFT 30
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#define FSR_RD_MASK 0x03
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#define FSR_RP 0x30000000 /* extended rounding precision */
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#define FSR_RP_X 0 /* extended stays extended */
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#define FSR_RP_S 1 /* extended => single */
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#define FSR_RP_D 2 /* extended => double */
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#define FSR_RP_80 3 /* extended => 80-bit */
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#define FSR_RP_SHIFT 28
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#define FSR_RP_MASK 0x03
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#define FSR_TEM 0x0f800000 /* trap enable mask */
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#define FSR_TEM_SHIFT 23
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#define FSR_TEM_MASK 0x1f
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#define FSR_NS 0x00400000 /* ``nonstandard mode'' */
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#define FSR_AU 0x00400000 /* aka abrupt underflow mode */
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#define FSR_MBZ 0x00300000 /* reserved; must be zero */
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#define FSR_VER 0x000e0000 /* version bits */
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#define FSR_VER_SHIFT 17
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#define FSR_VER_MASK 0x07
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#define FSR_FTT 0x0001c000 /* FP trap type */
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#define FSR_TT_NONE 0 /* no trap */
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#define FSR_TT_IEEE 1 /* IEEE exception */
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#define FSR_TT_UNFIN 2 /* unfinished operation */
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#define FSR_TT_UNIMP 3 /* unimplemented operation */
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#define FSR_TT_SEQ 4 /* sequence error */
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#define FSR_TT_HWERR 5 /* hardware error (unrecoverable) */
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#define FSR_FTT_SHIFT 14
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#define FSR_FTT_MASK 0x03
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#define FSR_QNE 0x00002000 /* queue not empty */
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#define FSR_PR 0x00001000 /* partial result */
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#define FSR_FCC 0x00000c00 /* FP condition codes */
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#define FSR_CC_EQ 0 /* f1 = f2 */
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#define FSR_CC_LT 1 /* f1 < f2 */
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#define FSR_CC_GT 2 /* f1 > f2 */
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#define FSR_CC_UO 3 /* (f1,f2) unordered */
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#define FSR_FCC_SHIFT 10
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#define FSR_FCC_MASK 0x03
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#define FSR_AX 0x000003e0 /* accrued exceptions */
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#define FSR_AX_SHIFT 5
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#define FSR_AX_MASK 0x1f
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#define FSR_CX 0x0000001f /* current exceptions */
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#define FSR_CX_SHIFT 0
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#define FSR_CX_MASK 0x1f
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/* These are the 3 new v9 fcc's */
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#define FSR_FCC3 0x06000000000 /* FP condition codes */
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#define FSR_FCC3_SHIFT 36
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#define FSR_FCC2 0x0c00000000 /* FP condition codes */
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#define FSR_FCC2_SHIFT 34
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#define FSR_FCC1 0x0600000000 /* FP condition codes */
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#define FSR_FCC1_SHIFT 32
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/* The following exceptions apply to TEM, AX, and CX. */
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#define FSR_NV 0x10 /* invalid operand */
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#define FSR_OF 0x08 /* overflow */
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#define FSR_UF 0x04 /* underflow */
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#define FSR_DZ 0x02 /* division by zero */
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#define FSR_NX 0x01 /* inexact result */
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#endif /* _MACHINE_FSR_H_ */
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