786 lines
27 KiB
C
786 lines
27 KiB
C
/**************************************************************************
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Copyright (c) 2007, Chelsio Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Neither the name of the Chelsio Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#ifndef __CHELSIO_COMMON_H
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#define __CHELSIO_COMMON_H
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#ifdef CONFIG_DEFINED
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#include <cxgb_osdep.h>
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#else
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#include <dev/pci/cxgb/cxgb_osdep.h>
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// ??? #include <dev/pci/cxgb/cxgb_toedev.h>
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#endif
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enum {
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MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
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EEPROMSIZE = 8192, /* Serial EEPROM size */
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SERNUM_LEN = 16, /* Serial # length */
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RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
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TCB_SIZE = 128, /* TCB size */
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NMTUS = 16, /* size of MTU table */
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NCCTRL_WIN = 32, /* # of congestion control windows */
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NTX_SCHED = 8, /* # of HW Tx scheduling queues */
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PROTO_SRAM_LINES = 128, /* size of protocol sram */
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MAX_NPORTS = 4,
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TP_TMR_RES = 200,
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TP_SRAM_OFFSET = 4096, /* TP SRAM content offset in eeprom */
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TP_SRAM_LEN = 2112, /* TP SRAM content offset in eeprom */
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};
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#define MAX_RX_COALESCING_LEN 12288U
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enum {
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PAUSE_RX = 1 << 0,
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PAUSE_TX = 1 << 1,
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PAUSE_AUTONEG = 1 << 2
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};
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enum {
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SUPPORTED_IRQ = 1 << 24
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};
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enum { /* adapter interrupt-maintained statistics */
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STAT_ULP_CH0_PBL_OOB,
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STAT_ULP_CH1_PBL_OOB,
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STAT_PCI_CORR_ECC,
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IRQ_NUM_STATS /* keep last */
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};
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enum {
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TP_VERSION_MAJOR = 1,
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TP_VERSION_MINOR = 1,
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TP_VERSION_MICRO = 0
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};
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#define S_TP_VERSION_MAJOR 16
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#define M_TP_VERSION_MAJOR 0xFF
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#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
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#define G_TP_VERSION_MAJOR(x) \
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(((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
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#define S_TP_VERSION_MINOR 8
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#define M_TP_VERSION_MINOR 0xFF
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#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR)
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#define G_TP_VERSION_MINOR(x) \
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(((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
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#define S_TP_VERSION_MICRO 0
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#define M_TP_VERSION_MICRO 0xFF
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#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
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#define G_TP_VERSION_MICRO(x) \
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(((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
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enum {
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FW_VERSION_MAJOR = 4,
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FW_VERSION_MINOR = 7,
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FW_VERSION_MICRO = 0
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};
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enum {
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SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
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SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
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SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
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};
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enum sge_context_type { /* SGE egress context types */
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SGE_CNTXT_RDMA = 0,
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SGE_CNTXT_ETH = 2,
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SGE_CNTXT_OFLD = 4,
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SGE_CNTXT_CTRL = 5
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};
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enum {
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AN_PKT_SIZE = 32, /* async notification packet size */
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IMMED_PKT_SIZE = 48 /* packet size for immediate data */
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};
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struct sg_ent { /* SGE scatter/gather entry */
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u32 len[2];
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u64 addr[2];
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};
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#ifndef SGE_NUM_GENBITS
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/* Must be 1 or 2 */
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# define SGE_NUM_GENBITS 2
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#endif
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#define TX_DESC_FLITS 16U
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#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
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struct cphy;
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struct mdio_ops {
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int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
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int reg_addr, unsigned int *val);
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int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
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int reg_addr, unsigned int val);
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};
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struct adapter_info {
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unsigned char nports0; /* # of ports on channel 0 */
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unsigned char nports1; /* # of ports on channel 1 */
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unsigned char phy_base_addr; /* MDIO PHY base address */
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unsigned char mdien:1;
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unsigned char mdiinv:1;
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unsigned int gpio_out; /* GPIO output settings */
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unsigned int gpio_intr; /* GPIO IRQ enable mask */
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unsigned long caps; /* adapter capabilities */
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const struct mdio_ops *mdio_ops; /* MDIO operations */
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const char *desc; /* product description */
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};
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struct port_type_info {
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void (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr,
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const struct mdio_ops *ops);
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unsigned int caps;
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const char *desc;
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};
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struct mc5_stats {
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unsigned long parity_err;
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unsigned long active_rgn_full;
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unsigned long nfa_srch_err;
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unsigned long unknown_cmd;
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unsigned long reqq_parity_err;
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unsigned long dispq_parity_err;
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unsigned long del_act_empty;
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};
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struct mc7_stats {
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unsigned long corr_err;
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unsigned long uncorr_err;
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unsigned long parity_err;
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unsigned long addr_err;
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};
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struct mac_stats {
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u64 tx_octets; /* total # of octets in good frames */
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u64 tx_octets_bad; /* total # of octets in error frames */
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u64 tx_frames; /* all good frames */
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u64 tx_mcast_frames; /* good multicast frames */
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u64 tx_bcast_frames; /* good broadcast frames */
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u64 tx_pause; /* # of transmitted pause frames */
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u64 tx_deferred; /* frames with deferred transmissions */
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u64 tx_late_collisions; /* # of late collisions */
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u64 tx_total_collisions; /* # of total collisions */
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u64 tx_excess_collisions; /* frame errors from excessive collissions */
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u64 tx_underrun; /* # of Tx FIFO underruns */
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u64 tx_len_errs; /* # of Tx length errors */
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u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
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u64 tx_excess_deferral; /* # of frames with excessive deferral */
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u64 tx_fcs_errs; /* # of frames with bad FCS */
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u64 tx_frames_64; /* # of Tx frames in a particular range */
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u64 tx_frames_65_127;
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u64 tx_frames_128_255;
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u64 tx_frames_256_511;
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u64 tx_frames_512_1023;
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u64 tx_frames_1024_1518;
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u64 tx_frames_1519_max;
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u64 rx_octets; /* total # of octets in good frames */
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u64 rx_octets_bad; /* total # of octets in error frames */
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u64 rx_frames; /* all good frames */
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u64 rx_mcast_frames; /* good multicast frames */
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u64 rx_bcast_frames; /* good broadcast frames */
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u64 rx_pause; /* # of received pause frames */
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u64 rx_fcs_errs; /* # of received frames with bad FCS */
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u64 rx_align_errs; /* alignment errors */
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u64 rx_symbol_errs; /* symbol errors */
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u64 rx_data_errs; /* data errors */
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u64 rx_sequence_errs; /* sequence errors */
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u64 rx_runt; /* # of runt frames */
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u64 rx_jabber; /* # of jabber frames */
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u64 rx_short; /* # of short frames */
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u64 rx_too_long; /* # of oversized frames */
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u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
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u64 rx_frames_64; /* # of Rx frames in a particular range */
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u64 rx_frames_65_127;
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u64 rx_frames_128_255;
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u64 rx_frames_256_511;
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u64 rx_frames_512_1023;
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u64 rx_frames_1024_1518;
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u64 rx_frames_1519_max;
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u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
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unsigned long tx_fifo_parity_err;
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unsigned long rx_fifo_parity_err;
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unsigned long tx_fifo_urun;
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unsigned long rx_fifo_ovfl;
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unsigned long serdes_signal_loss;
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unsigned long xaui_pcs_ctc_err;
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unsigned long xaui_pcs_align_change;
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unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
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unsigned long num_resets; /* # times reset due to stuck TX */
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};
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struct tp_mib_stats {
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u32 ipInReceive_hi;
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u32 ipInReceive_lo;
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u32 ipInHdrErrors_hi;
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u32 ipInHdrErrors_lo;
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u32 ipInAddrErrors_hi;
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u32 ipInAddrErrors_lo;
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u32 ipInUnknownProtos_hi;
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u32 ipInUnknownProtos_lo;
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u32 ipInDiscards_hi;
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u32 ipInDiscards_lo;
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u32 ipInDelivers_hi;
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u32 ipInDelivers_lo;
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u32 ipOutRequests_hi;
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u32 ipOutRequests_lo;
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u32 ipOutDiscards_hi;
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u32 ipOutDiscards_lo;
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u32 ipOutNoRoutes_hi;
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u32 ipOutNoRoutes_lo;
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u32 ipReasmTimeout;
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u32 ipReasmReqds;
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u32 ipReasmOKs;
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u32 ipReasmFails;
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u32 reserved[8];
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u32 tcpActiveOpens;
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u32 tcpPassiveOpens;
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u32 tcpAttemptFails;
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u32 tcpEstabResets;
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u32 tcpOutRsts;
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u32 tcpCurrEstab;
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u32 tcpInSegs_hi;
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u32 tcpInSegs_lo;
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u32 tcpOutSegs_hi;
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u32 tcpOutSegs_lo;
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u32 tcpRetransSeg_hi;
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u32 tcpRetransSeg_lo;
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u32 tcpInErrs_hi;
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u32 tcpInErrs_lo;
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u32 tcpRtoMin;
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u32 tcpRtoMax;
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};
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struct tp_params {
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unsigned int nchan; /* # of channels */
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unsigned int pmrx_size; /* total PMRX capacity */
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unsigned int pmtx_size; /* total PMTX capacity */
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unsigned int cm_size; /* total CM capacity */
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unsigned int chan_rx_size; /* per channel Rx size */
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unsigned int chan_tx_size; /* per channel Tx size */
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unsigned int rx_pg_size; /* Rx page size */
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unsigned int tx_pg_size; /* Tx page size */
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unsigned int rx_num_pgs; /* # of Rx pages */
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unsigned int tx_num_pgs; /* # of Tx pages */
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unsigned int ntimer_qs; /* # of timer queues */
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unsigned int tre; /* log2 of core clocks per TP tick */
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unsigned int dack_re; /* DACK timer resolution */
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};
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struct qset_params { /* SGE queue set parameters */
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unsigned int polling; /* polling/interrupt service for rspq */
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unsigned int lro; /* large receive offload */
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unsigned int coalesce_nsecs; /* irq coalescing timer */
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unsigned int rspq_size; /* # of entries in response queue */
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unsigned int fl_size; /* # of entries in regular free list */
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unsigned int jumbo_size; /* # of entries in jumbo free list */
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unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
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unsigned int cong_thres; /* FL congestion threshold */
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unsigned int vector; /* Interrupt (line or vector) number */
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};
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struct sge_params {
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unsigned int max_pkt_size; /* max offload pkt size */
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struct qset_params qset[SGE_QSETS];
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};
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struct mc5_params {
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unsigned int mode; /* selects MC5 width */
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unsigned int nservers; /* size of server region */
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unsigned int nfilters; /* size of filter region */
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unsigned int nroutes; /* size of routing region */
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};
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/* Default MC5 region sizes */
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enum {
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DEFAULT_NSERVERS = 512,
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DEFAULT_NFILTERS = 128
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};
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/* MC5 modes, these must be non-0 */
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enum {
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MC5_MODE_144_BIT = 1,
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MC5_MODE_72_BIT = 2
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};
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/* MC5 min active region size */
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enum { MC5_MIN_TIDS = 16 };
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struct vpd_params {
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unsigned int cclk;
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unsigned int mclk;
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unsigned int uclk;
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unsigned int mdc;
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unsigned int mem_timing;
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u8 sn[SERNUM_LEN + 1];
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u8 eth_base[6];
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u8 port_type[MAX_NPORTS];
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unsigned short xauicfg[2];
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};
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struct pci_params {
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unsigned int vpd_cap_addr;
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unsigned int pcie_cap_addr;
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unsigned short speed;
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unsigned char width;
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unsigned char variant;
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};
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enum {
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PCI_VARIANT_PCI,
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PCI_VARIANT_PCIX_MODE1_PARITY,
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PCI_VARIANT_PCIX_MODE1_ECC,
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PCI_VARIANT_PCIX_266_MODE2,
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PCI_VARIANT_PCIE
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};
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struct adapter_params {
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struct sge_params sge;
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struct mc5_params mc5;
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struct tp_params tp;
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struct vpd_params vpd;
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struct pci_params pci;
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const struct adapter_info *info;
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#ifdef CONFIG_CHELSIO_T3_CORE
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unsigned short mtus[NMTUS];
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unsigned short a_wnd[NCCTRL_WIN];
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unsigned short b_wnd[NCCTRL_WIN];
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#endif
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unsigned int nports; /* # of ethernet ports */
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unsigned int chan_map; /* bitmap of in-use Tx channels */
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unsigned int stats_update_period; /* MAC stats accumulation period */
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unsigned int linkpoll_period; /* link poll period in 0.1s */
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unsigned int rev; /* chip revision */
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unsigned int offload;
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};
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enum { /* chip revisions */
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T3_REV_A = 0,
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T3_REV_B = 2,
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T3_REV_B2 = 3,
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T3_REV_C = 4,
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};
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struct trace_params {
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u32 sip;
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u32 sip_mask;
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u32 dip;
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u32 dip_mask;
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u16 sport;
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u16 sport_mask;
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u16 dport;
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u16 dport_mask;
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u32 vlan:12;
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u32 vlan_mask:12;
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u32 intf:4;
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u32 intf_mask:4;
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u8 proto;
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u8 proto_mask;
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};
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struct link_config {
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unsigned int supported; /* link capabilities */
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unsigned int advertising; /* advertised capabilities */
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unsigned short requested_speed; /* speed user has requested */
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unsigned short speed; /* actual link speed */
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unsigned char requested_duplex; /* duplex user has requested */
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unsigned char duplex; /* actual link duplex */
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unsigned char requested_fc; /* flow control user has requested */
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unsigned char fc; /* actual link flow control */
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unsigned char autoneg; /* autonegotiating? */
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unsigned int link_ok; /* link up? */
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};
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#define SPEED_INVALID 0xffff
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#define DUPLEX_INVALID 0xff
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struct mc5 {
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adapter_t *adapter;
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unsigned int tcam_size;
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unsigned char part_type;
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unsigned char parity_enabled;
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unsigned char mode;
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struct mc5_stats stats;
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};
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static __inline unsigned int t3_mc5_size(const struct mc5 *p)
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{
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return p->tcam_size;
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}
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struct mc7 {
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adapter_t *adapter; /* backpointer to adapter */
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unsigned int size; /* memory size in bytes */
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unsigned int width; /* MC7 interface width */
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unsigned int offset; /* register address offset for MC7 instance */
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const char *name; /* name of MC7 instance */
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struct mc7_stats stats; /* MC7 statistics */
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};
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static __inline unsigned int t3_mc7_size(const struct mc7 *p)
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{
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return p->size;
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}
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struct cmac {
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adapter_t *adapter;
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unsigned int offset;
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unsigned char nucast; /* # of address filters for unicast MACs */
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unsigned char multiport; /* multiple ports connected to this MAC */
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unsigned char ext_port; /* external MAC port */
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unsigned char promisc_map; /* which external ports are promiscuous */
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unsigned int tx_tcnt;
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unsigned int tx_xcnt;
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u64 tx_mcnt;
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unsigned int rx_xcnt;
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unsigned int rx_ocnt;
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u64 rx_mcnt;
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unsigned int toggle_cnt;
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unsigned int txen;
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u64 rx_pause;
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struct mac_stats stats;
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};
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enum {
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MAC_DIRECTION_RX = 1,
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MAC_DIRECTION_TX = 2,
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MAC_RXFIFO_SIZE = 32768
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};
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|
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/* IEEE 802.3ae specified MDIO devices */
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enum {
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MDIO_DEV_PMA_PMD = 1,
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MDIO_DEV_WIS = 2,
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MDIO_DEV_PCS = 3,
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MDIO_DEV_XGXS = 4
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};
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|
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/* PHY loopback direction */
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enum {
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PHY_LOOPBACK_TX = 1,
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PHY_LOOPBACK_RX = 2
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};
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|
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/* PHY interrupt types */
|
|
enum {
|
|
cphy_cause_link_change = 1,
|
|
cphy_cause_fifo_error = 2
|
|
};
|
|
|
|
/* PHY operations */
|
|
struct cphy_ops {
|
|
void (*destroy)(struct cphy *phy);
|
|
int (*reset)(struct cphy *phy, int wait);
|
|
|
|
int (*intr_enable)(struct cphy *phy);
|
|
int (*intr_disable)(struct cphy *phy);
|
|
int (*intr_clear)(struct cphy *phy);
|
|
int (*intr_handler)(struct cphy *phy);
|
|
|
|
int (*autoneg_enable)(struct cphy *phy);
|
|
int (*autoneg_restart)(struct cphy *phy);
|
|
|
|
int (*advertise)(struct cphy *phy, unsigned int advertise_map);
|
|
int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
|
|
int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
|
|
int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
|
|
int *duplex, int *fc);
|
|
int (*power_down)(struct cphy *phy, int enable);
|
|
};
|
|
|
|
/* A PHY instance */
|
|
struct cphy {
|
|
int addr; /* PHY address */
|
|
adapter_t *adapter; /* associated adapter */
|
|
unsigned long fifo_errors; /* FIFO over/under-flows */
|
|
const struct cphy_ops *ops; /* PHY operations */
|
|
int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
|
int reg_addr, unsigned int *val);
|
|
int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
|
|
int reg_addr, unsigned int val);
|
|
};
|
|
|
|
/* Convenience MDIO read/write wrappers */
|
|
static __inline int mdio_read(struct cphy *phy, int mmd, int reg,
|
|
unsigned int *valp)
|
|
{
|
|
return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
|
|
}
|
|
|
|
static __inline int mdio_write(struct cphy *phy, int mmd, int reg,
|
|
unsigned int val)
|
|
{
|
|
return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
|
|
}
|
|
|
|
/* Convenience initializer */
|
|
static __inline void cphy_init(struct cphy *phy, adapter_t *adapter,
|
|
int phy_addr, struct cphy_ops *phy_ops,
|
|
const struct mdio_ops *mdio_ops)
|
|
{
|
|
phy->adapter = adapter;
|
|
phy->addr = phy_addr;
|
|
phy->ops = phy_ops;
|
|
if (mdio_ops) {
|
|
phy->mdio_read = mdio_ops->read;
|
|
phy->mdio_write = mdio_ops->write;
|
|
}
|
|
}
|
|
|
|
/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
|
|
#define MAC_STATS_ACCUM_SECS 180
|
|
|
|
/* The external MAC needs accumulation every 30 seconds */
|
|
#define VSC_STATS_ACCUM_SECS 30
|
|
|
|
#define XGM_REG(reg_addr, idx) \
|
|
((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
|
|
|
|
struct addr_val_pair {
|
|
unsigned int reg_addr;
|
|
unsigned int val;
|
|
};
|
|
|
|
#ifdef CONFIG_DEFINED
|
|
#include <cxgb_adapter.h>
|
|
#else
|
|
#include <dev/pci/cxgb/cxgb_adapter.h>
|
|
#endif
|
|
|
|
#ifndef PCI_VENDOR_ID_CHELSIO
|
|
# define PCI_VENDOR_ID_CHELSIO 0x1425
|
|
#endif
|
|
|
|
#define for_each_port(adapter, iter) \
|
|
for (iter = 0; iter < (adapter)->params.nports; ++iter)
|
|
|
|
#define adapter_info(adap) ((adap)->params.info)
|
|
|
|
static __inline int uses_xaui(const adapter_t *adap)
|
|
{
|
|
return adapter_info(adap)->caps & SUPPORTED_AUI;
|
|
}
|
|
|
|
static __inline int is_10G(const adapter_t *adap)
|
|
{
|
|
return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
|
|
}
|
|
|
|
static __inline int is_offload(const adapter_t *adap)
|
|
{
|
|
#ifdef CONFIG_CHELSIO_T3_CORE
|
|
return adap->params.offload;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
static __inline unsigned int core_ticks_per_usec(const adapter_t *adap)
|
|
{
|
|
return adap->params.vpd.cclk / 1000;
|
|
}
|
|
|
|
static __inline unsigned int dack_ticks_to_usec(const adapter_t *adap,
|
|
unsigned int ticks)
|
|
{
|
|
return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
|
|
}
|
|
|
|
static __inline unsigned int is_pcie(const adapter_t *adap)
|
|
{
|
|
return adap->params.pci.variant == PCI_VARIANT_PCIE;
|
|
}
|
|
|
|
void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
|
|
void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
|
|
unsigned int offset);
|
|
int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
|
|
int attempts, int delay, u32 *valp);
|
|
|
|
static __inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,
|
|
int polarity, int attempts, int delay)
|
|
{
|
|
return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
|
|
delay, NULL);
|
|
}
|
|
|
|
int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
|
|
unsigned int set);
|
|
int t3_phy_reset(struct cphy *phy, int mmd, int wait);
|
|
int t3_phy_advertise(struct cphy *phy, unsigned int advert);
|
|
int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
|
|
|
|
void t3_intr_enable(adapter_t *adapter);
|
|
void t3_intr_disable(adapter_t *adapter);
|
|
void t3_intr_clear(adapter_t *adapter);
|
|
void t3_port_intr_enable(adapter_t *adapter, int idx);
|
|
void t3_port_intr_disable(adapter_t *adapter, int idx);
|
|
void t3_port_intr_clear(adapter_t *adapter, int idx);
|
|
int t3_slow_intr_handler(adapter_t *adapter);
|
|
int t3_phy_intr_handler(adapter_t *adapter);
|
|
|
|
void t3_link_changed(adapter_t *adapter, int port_id);
|
|
int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
|
|
const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
|
|
int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
|
|
int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
|
|
int t3_seeprom_wp(adapter_t *adapter, int enable);
|
|
int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
|
|
u32 *data, int byte_oriented);
|
|
int t3_get_tp_version(adapter_t *adapter, u32 *vers);
|
|
int t3_check_tpsram_version(adapter_t *adapter);
|
|
int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
|
|
int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
|
|
int t3_get_fw_version(adapter_t *adapter, u32 *vers);
|
|
int t3_check_fw_version(adapter_t *adapter);
|
|
int t3_init_hw(adapter_t *adapter, u32 fw_params);
|
|
void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
|
|
void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
|
|
int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
|
|
void t3_led_ready(adapter_t *adapter);
|
|
void t3_fatal_err(adapter_t *adapter);
|
|
void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
|
|
void t3_enable_filters(adapter_t *adap);
|
|
void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
|
|
const u16 *rspq);
|
|
int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
|
|
int t3_set_proto_sram(adapter_t *adap, const u8 *data);
|
|
int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
|
|
void t3_port_failover(adapter_t *adapter, int port);
|
|
void t3_failover_done(adapter_t *adapter, int port);
|
|
void t3_failover_clear(adapter_t *adapter);
|
|
int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
|
|
unsigned int *valp);
|
|
int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
|
|
u64 *buf);
|
|
|
|
int t3_mac_reset(struct cmac *mac);
|
|
void t3b_pcs_reset(struct cmac *mac);
|
|
int t3_mac_enable(struct cmac *mac, int which);
|
|
int t3_mac_disable(struct cmac *mac, int which);
|
|
int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
|
|
int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
|
|
int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
|
|
int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n);
|
|
const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
|
|
int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
|
|
int fc);
|
|
int t3b2_mac_watchdog_task(struct cmac *mac);
|
|
|
|
void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
|
|
int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
|
|
unsigned int nroutes);
|
|
void t3_mc5_intr_handler(struct mc5 *mc5);
|
|
int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
|
|
u32 *buf);
|
|
|
|
#ifdef CONFIG_CHELSIO_T3_CORE
|
|
int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
|
|
void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
|
|
void t3_tp_set_offload_mode(adapter_t *adap, int enable);
|
|
void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
|
|
void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
|
|
unsigned short alpha[NCCTRL_WIN],
|
|
unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
|
|
void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
|
|
void t3_get_cong_cntl_tab(adapter_t *adap,
|
|
unsigned short incr[NMTUS][NCCTRL_WIN]);
|
|
void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
|
|
int filter_index, int invert, int enable);
|
|
int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
|
|
int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);
|
|
void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
|
|
unsigned int *ipg);
|
|
void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]);
|
|
void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
|
|
unsigned int start, unsigned int n);
|
|
#endif
|
|
|
|
void t3_sge_prep(adapter_t *adap, struct sge_params *p);
|
|
void t3_sge_init(adapter_t *adap, struct sge_params *p);
|
|
int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
|
|
enum sge_context_type type, int respq, u64 base_addr,
|
|
unsigned int size, unsigned int token, int gen,
|
|
unsigned int cidx);
|
|
int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
|
|
u64 base_addr, unsigned int size, unsigned int esize,
|
|
unsigned int cong_thres, int gen, unsigned int cidx);
|
|
int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
|
|
u64 base_addr, unsigned int size,
|
|
unsigned int fl_thres, int gen, unsigned int cidx);
|
|
int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
|
|
unsigned int size, int rspq, int ovfl_mode,
|
|
unsigned int credits, unsigned int credit_thres);
|
|
int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable);
|
|
int t3_sge_disable_fl(adapter_t *adapter, unsigned int id);
|
|
int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id);
|
|
int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id);
|
|
int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]);
|
|
int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]);
|
|
int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]);
|
|
int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
|
|
int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
|
|
unsigned int credits);
|
|
|
|
int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
|
|
int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
|
|
int t3_vsc7323_init(adapter_t *adap, int nports);
|
|
int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
|
|
int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
|
|
int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
|
|
int t3_vsc7323_enable(adapter_t *adap, int port, int which);
|
|
int t3_vsc7323_disable(adapter_t *adap, int port, int which);
|
|
const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
|
|
|
|
void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
|
const struct mdio_ops *mdio_ops);
|
|
void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
|
const struct mdio_ops *mdio_ops);
|
|
void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
|
const struct mdio_ops *mdio_ops);
|
|
void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
|
const struct mdio_ops *mdio_ops);
|
|
void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
|
const struct mdio_ops *mdio_ops);
|
|
void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
|
|
const struct mdio_ops *mdio_ops);
|
|
#endif /* __CHELSIO_COMMON_H */
|