1308c6d767
by the isa.c bus driver and the "address/whatever not specified" argument passed to leaf device drivers. The former is "ISACF_XXX_DEFAULT" as generaterd by config(8), the latter "ISA_UNKNOWN_XXX", defined in isavar.h. This way we save a dependency of every ISA device driver on "locators.h".
616 lines
17 KiB
C
616 lines
17 KiB
C
/* $NetBSD: esp_isa.c,v 1.28 2004/09/14 20:20:46 drochner Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
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* Simulation Facility, NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994 Peter Galbavy
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Based on aic6360 by Jarle Greipsland
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*
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* Acknowledgements: Many of the algorithms used in this driver are
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* inspired by the work of Julian Elischer (julian@tfs.com) and
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* Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
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*/
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/*
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* Initial m68k mac support from Allen Briggs <briggs@macbsd.com>
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* (basically consisting of the match, a bit of the attach, and the
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* "DMA" glue functions).
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*/
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/*
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* Copyright (c) 1997 Eric S. Hvozda (hvozda@netcom.com)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Eric S. Hvozda.
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* 4. The name of Eric S. Hvozda may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: esp_isa.c,v 1.28 2004/09/14 20:20:46 drochner Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/isa/isavar.h>
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#include <dev/isa/isadmavar.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <dev/isa/esp_isavar.h>
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int esp_isa_match __P((struct device *, struct cfdata *, void *));
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void esp_isa_attach __P((struct device *, struct device *, void *));
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CFATTACH_DECL(esp_isa, sizeof(struct esp_isa_softc),
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esp_isa_match, esp_isa_attach, NULL, NULL);
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int esp_isa_debug = 0; /* ESP_SHOWTRAC | ESP_SHOWREGS | ESP_SHOWMISC */
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/*
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* Functions and the switch for the MI code.
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*/
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u_char esp_isa_read_reg __P((struct ncr53c9x_softc *, int));
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void esp_isa_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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int esp_isa_dma_isintr __P((struct ncr53c9x_softc *));
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void esp_isa_dma_reset __P((struct ncr53c9x_softc *));
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int esp_isa_dma_intr __P((struct ncr53c9x_softc *));
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int esp_isa_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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void esp_isa_dma_go __P((struct ncr53c9x_softc *));
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void esp_isa_dma_stop __P((struct ncr53c9x_softc *));
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int esp_isa_dma_isactive __P((struct ncr53c9x_softc *));
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struct ncr53c9x_glue esp_isa_glue = {
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esp_isa_read_reg,
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esp_isa_write_reg,
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esp_isa_dma_isintr,
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esp_isa_dma_reset,
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esp_isa_dma_intr,
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esp_isa_dma_setup,
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esp_isa_dma_go,
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esp_isa_dma_stop,
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esp_isa_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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/*
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* Look for the board
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*/
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int
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esp_isa_find(iot, ioh, epd)
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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struct esp_isa_probe_data *epd;
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{
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u_int vers;
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u_int p1;
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u_int p2;
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u_int jmp;
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ESP_TRACE(("[esp_isa_find] "));
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/* reset card before we probe? */
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epd->sc_cfg4 = NCRCFG4_ACTNEG;
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epd->sc_cfg5 = NCRCFG5_CRS1 | NCRCFG5_AADDR | NCRCFG5_PTRINC;
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/*
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* Switch to the PIO regs and look for the bit pattern
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* we expect...
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*/
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bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5);
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#define SIG_MASK 0x87
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#define REV_MASK 0x70
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#define M1 0x02
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#define M2 0x05
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#define ISNCR 0x80
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#define ISESP406 0x40
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vers = bus_space_read_1(iot, ioh, NCR_SIGNTR);
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p1 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK;
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p2 = bus_space_read_1(iot, ioh, NCR_SIGNTR) & SIG_MASK;
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ESP_MISC(("esp_isa_find: 0x%0x 0x%0x 0x%0x\n", vers, p1, p2));
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if (!((p1 == M1 && p2 == M2) || (p1 == M2 && p2 == M1)))
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return 0;
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/* Ok, what is it? */
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epd->sc_isncr = (vers & ISNCR);
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epd->sc_rev = ((vers & REV_MASK) == ISESP406) ?
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NCR_VARIANT_ESP406 : NCR_VARIANT_FAS408;
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/* What do the jumpers tell us? */
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jmp = bus_space_read_1(iot, ioh, NCR_JMP);
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epd->sc_msize = (jmp & NCRJMP_ROMSZ) ? 0x4000 : 0x8000;
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epd->sc_parity = jmp & NCRJMP_J2;
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epd->sc_sync = jmp & NCRJMP_J4;
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epd->sc_id = (jmp & NCRJMP_J3) ? 7 : 6;
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switch (jmp & (NCRJMP_J0 | NCRJMP_J1)) {
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case NCRJMP_J0 | NCRJMP_J1:
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epd->sc_irq = 11;
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break;
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case NCRJMP_J0:
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epd->sc_irq = 10;
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break;
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case NCRJMP_J1:
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epd->sc_irq = 15;
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break;
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default:
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epd->sc_irq = 12;
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break;
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}
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bus_space_write_1(iot, ioh, NCR_CFG5, epd->sc_cfg5);
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/* Try to set NCRESPCFG3_FCLK, some FAS408's don't support
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* NCRESPCFG3_FCLK even though it is documented. A bad
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* batch of chips perhaps?
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*/
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bus_space_write_1(iot, ioh, NCR_ESPCFG3,
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bus_space_read_1(iot, ioh, NCR_ESPCFG3) | NCRESPCFG3_FCLK);
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epd->sc_isfast = bus_space_read_1(iot, ioh, NCR_ESPCFG3)
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& NCRESPCFG3_FCLK;
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return 1;
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}
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void
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esp_isa_init(esc, epd)
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struct esp_isa_softc *esc;
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struct esp_isa_probe_data *epd;
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{
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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ESP_TRACE(("[esp_isa_init] "));
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/*
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* Set up the glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &esp_isa_glue;
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sc->sc_rev = epd->sc_rev;
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sc->sc_id = epd->sc_id;
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/* If we could set NCRESPCFG3_FCLK earlier, we can really move */
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sc->sc_cfg3 = NCR_READ_REG(sc, NCR_ESPCFG3);
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if ((epd->sc_rev == NCR_VARIANT_FAS408) && epd->sc_isfast) {
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sc->sc_freq = 40;
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sc->sc_cfg3 |= NCRESPCFG3_FCLK;
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} else
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sc->sc_freq = 24;
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/* Setup the register defaults */
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sc->sc_cfg1 = sc->sc_id;
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if (epd->sc_parity)
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sc->sc_cfg1 |= NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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sc->sc_cfg3 |= NCRESPCFG3_IDM | NCRESPCFG3_FSCSI;
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sc->sc_cfg4 = epd->sc_cfg4;
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sc->sc_cfg5 = epd->sc_cfg5;
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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if (epd->sc_sync)
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{
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#ifdef DIAGNOSTIC
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printf("%s: sync requested, but not supported; will do async\n",
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sc->sc_dev.dv_xname);
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#endif
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epd->sc_sync = 0;
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}
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sc->sc_minsync = 0;
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/* Really no limit, but since we want to fit into the TCR... */
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sc->sc_maxxfer = 64 * 1024;
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}
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/*
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* Check the slots looking for a board we recognise
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* If we find one, note it's address (slot) and call
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* the actual probe routine to check it out.
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*/
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int
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esp_isa_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct isa_attach_args *ia = aux;
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bus_space_tag_t iot = ia->ia_iot;
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bus_space_handle_t ioh;
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struct esp_isa_probe_data epd;
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int rv;
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if (ia->ia_nio < 1)
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return (0);
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if (ia->ia_nirq < 1)
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return (0);
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if (ia->ia_ndrq < 1)
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return (0);
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if (ISA_DIRECT_CONFIG(ia))
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return (0);
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ESP_TRACE(("[esp_isa_match] "));
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if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
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return 0;
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if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh))
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return 0;
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rv = esp_isa_find(iot, ioh, &epd);
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bus_space_unmap(iot, ioh, ESP_ISA_IOSIZE);
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if (rv) {
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if (ia->ia_irq[0].ir_irq != ISA_UNKNOWN_IRQ &&
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ia->ia_irq[0].ir_irq != epd.sc_irq) {
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#ifdef DIAGNOSTIC
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printf("esp_isa_match: configured IRQ (%0d) does not "
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"match board IRQ (%0d), device not configured\n",
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ia->ia_irq[0].ir_irq, epd.sc_irq);
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#endif
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return 0;
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}
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ia->ia_irq[0].ir_irq = epd.sc_irq;
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ia->ia_iomem[0].ir_size = 0;
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ia->ia_io[0].ir_size = ESP_ISA_IOSIZE;
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}
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return (rv);
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}
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/*
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* Attach this instance, and then all the sub-devices
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*/
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void
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esp_isa_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct isa_attach_args *ia = aux;
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struct esp_isa_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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bus_space_tag_t iot = ia->ia_iot;
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bus_space_handle_t ioh;
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struct esp_isa_probe_data epd;
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isa_chipset_tag_t ic = ia->ia_ic;
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int error;
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printf("\n");
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ESP_TRACE(("[esp_isa_attach] "));
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if (bus_space_map(iot, ia->ia_io[0].ir_addr, ESP_ISA_IOSIZE, 0, &ioh)) {
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printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname);
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return;
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}
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if (!esp_isa_find(iot, ioh, &epd)) {
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printf("%s: esp_isa_find failed\n", sc->sc_dev.dv_xname);
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return;
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}
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if (ia->ia_drq[0].ir_drq != ISA_UNKNOWN_DRQ) {
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if ((error = isa_dmacascade(ic, ia->ia_drq[0].ir_drq)) != 0) {
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printf("%s: unable to cascade DRQ, error = %d\n",
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sc->sc_dev.dv_xname, error);
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return;
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}
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}
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esc->sc_ih = isa_intr_establish(ic, ia->ia_irq[0].ir_irq, IST_EDGE,
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IPL_BIO, ncr53c9x_intr, esc);
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if (esc->sc_ih == NULL) {
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printf("%s: couldn't establish interrupt\n",
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sc->sc_dev.dv_xname);
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return;
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}
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esc->sc_ioh = ioh;
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esc->sc_iot = iot;
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esp_isa_init(esc, &epd);
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printf("%s:%ssync,%sparity\n", sc->sc_dev.dv_xname,
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epd.sc_sync ? " " : " no ", epd.sc_parity ? " " : " no ");
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printf("%s", sc->sc_dev.dv_xname);
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/*
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* Now try to attach all the sub-devices
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*/
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sc->sc_adapter.adapt_minphys = minphys;
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sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
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ncr53c9x_attach(sc);
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}
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/*
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* Glue functions.
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*/
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u_char
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esp_isa_read_reg(sc, reg)
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struct ncr53c9x_softc *sc;
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int reg;
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{
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struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
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u_char v;
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v = bus_space_read_1(esc->sc_iot, esc->sc_ioh, reg);
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ESP_REGS(("[esp_isa_read_reg CRS%c 0x%02x=0x%02x] ",
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(bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) &
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NCRCFG4_CRS1) ? '1' : '0', reg, v));
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return v;
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}
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|
|
|
void
|
|
esp_isa_write_reg(sc, reg, val)
|
|
struct ncr53c9x_softc *sc;
|
|
int reg;
|
|
u_char val;
|
|
{
|
|
struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
|
|
u_char v = val;
|
|
|
|
if (reg == NCR_CMD && v == (NCRCMD_TRANS|NCRCMD_DMA)) {
|
|
v = NCRCMD_TRANS;
|
|
}
|
|
|
|
ESP_REGS(("[esp_isa_write_reg CRS%c 0x%02x=0x%02x] ",
|
|
(bus_space_read_1(esc->sc_iot, esc->sc_ioh, NCR_CFG4) &
|
|
NCRCFG4_CRS1) ? '1' : '0', reg, v));
|
|
|
|
bus_space_write_1(esc->sc_iot, esc->sc_ioh, reg, v);
|
|
}
|
|
|
|
int
|
|
esp_isa_dma_isintr(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
ESP_TRACE(("[esp_isa_dma_isintr] "));
|
|
|
|
return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT;
|
|
}
|
|
|
|
void
|
|
esp_isa_dma_reset(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
|
|
|
|
ESP_TRACE(("[esp_isa_dma_reset] "));
|
|
|
|
esc->sc_active = 0;
|
|
esc->sc_tc = 0;
|
|
}
|
|
|
|
int
|
|
esp_isa_dma_intr(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
|
|
u_char *p;
|
|
u_int espphase, espstat, espintr;
|
|
int cnt;
|
|
|
|
ESP_TRACE(("[esp_isa_dma_intr] "));
|
|
|
|
if (esc->sc_active == 0) {
|
|
printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname);
|
|
return -1;
|
|
}
|
|
|
|
if ((sc->sc_espintr & NCRINTR_BS) == 0) {
|
|
esc->sc_active = 0;
|
|
return 0;
|
|
}
|
|
|
|
cnt = *esc->sc_pdmalen;
|
|
if (*esc->sc_pdmalen == 0) {
|
|
printf("%s: data interrupt, but no count left\n",
|
|
sc->sc_dev.dv_xname);
|
|
}
|
|
|
|
p = *esc->sc_dmaaddr;
|
|
espphase = sc->sc_phase;
|
|
espstat = (u_int) sc->sc_espstat;
|
|
espintr = (u_int) sc->sc_espintr;
|
|
do {
|
|
if (esc->sc_datain) {
|
|
*p++ = NCR_READ_REG(sc, NCR_FIFO);
|
|
cnt--;
|
|
if (espphase == DATA_IN_PHASE) {
|
|
NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS);
|
|
} else {
|
|
esc->sc_active = 0;
|
|
}
|
|
} else {
|
|
if ( (espphase == DATA_OUT_PHASE)
|
|
|| (espphase == MESSAGE_OUT_PHASE)) {
|
|
NCR_WRITE_REG(sc, NCR_FIFO, *p++);
|
|
cnt--;
|
|
NCR_WRITE_REG(sc, NCR_CMD, NCRCMD_TRANS);
|
|
} else {
|
|
esc->sc_active = 0;
|
|
}
|
|
}
|
|
|
|
if (esc->sc_active) {
|
|
while (!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT));
|
|
espstat = NCR_READ_REG(sc, NCR_STAT);
|
|
espintr = NCR_READ_REG(sc, NCR_INTR);
|
|
espphase = (espintr & NCRINTR_DIS)
|
|
? /* Disconnected */ BUSFREE_PHASE
|
|
: espstat & PHASE_MASK;
|
|
}
|
|
} while (esc->sc_active && espintr);
|
|
sc->sc_phase = espphase;
|
|
sc->sc_espstat = (u_char) espstat;
|
|
sc->sc_espintr = (u_char) espintr;
|
|
*esc->sc_dmaaddr = p;
|
|
*esc->sc_pdmalen = cnt;
|
|
|
|
if (*esc->sc_pdmalen == 0) {
|
|
esc->sc_tc = NCRSTAT_TC;
|
|
}
|
|
sc->sc_espstat |= esc->sc_tc;
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
esp_isa_dma_setup(sc, addr, len, datain, dmasize)
|
|
struct ncr53c9x_softc *sc;
|
|
caddr_t *addr;
|
|
size_t *len;
|
|
int datain;
|
|
size_t *dmasize;
|
|
{
|
|
struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
|
|
|
|
ESP_TRACE(("[esp_isa_dma_setup] "));
|
|
|
|
esc->sc_dmaaddr = addr;
|
|
esc->sc_pdmalen = len;
|
|
esc->sc_datain = datain;
|
|
esc->sc_dmasize = *dmasize;
|
|
esc->sc_tc = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
esp_isa_dma_go(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
|
|
|
|
ESP_TRACE(("[esp_isa_dma_go] "));
|
|
|
|
esc->sc_active = 1;
|
|
}
|
|
|
|
void
|
|
esp_isa_dma_stop(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
ESP_TRACE(("[esp_isa_dma_stop] "));
|
|
}
|
|
|
|
int
|
|
esp_isa_dma_isactive(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct esp_isa_softc *esc = (struct esp_isa_softc *)sc;
|
|
|
|
ESP_TRACE(("[esp_isa_dma_isactive] "));
|
|
|
|
return esc->sc_active;
|
|
}
|