153 lines
4.6 KiB
C
153 lines
4.6 KiB
C
/* $NetBSD: plumvideoreg.h,v 1.1 1999/11/21 06:50:27 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/* (CS3) */
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#define PLUM_VIDEO_REGBASE 0x1000
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#define PLUM_VIDEO_REGSIZE 0x200
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/* (MCS0) */
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/* VRAM 4MByte */
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#define PLUM_VIDEO_VRAM_IOBASE 0x00000000
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#define PLUM_VIDEO_VRAM_IOSIZE 0x00400000
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/* Color palette LCD 4KByte */
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#define PLUM_VIDEO_CLUT_LCD_IOBASE 0x00400000
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#define PLUM_VIDEO_CLUT_LCD_IOSIZE 0x00001000
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/* Color palette CRT 4KByte */
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#define PLUM_VIDEO_CLUT_CRT_IOBASE 0x00401000
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#define PLUM_VIDEO_CLUT_CRT_IOSIZE 0x00001000
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/* BitBlt 4KByte */
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#define PLUM_VIDEO_BITBLT_IOBASE 0x00402000
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#define PLUM_VIDEO_BITBLT_IOSIZE 0x00401000
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/*
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* Common Control Register
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*/
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/* Interrupt Status enable and IRQ line enable */
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#define PLUM_VIDEO_POSENIEN_REG 0x000
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/* Interrupt Status */
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#define PLUM_VIDEO_POIST_REG 0x004
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/* Buffer Control */
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#define PLUM_VIDEO_POBFC_REG 0x008
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/* VRAM Control */
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#define PLUM_VIDEO_PORAM_REG 0x00c
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/* VRAM Refresh Control */
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#define PLUM_VIDEO_POREF_REG 0x010
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/* LCD Clock Source select and control */
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#define PLUM_VIDEO_POCKL_REG 0x014
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/* CRT Clock Source select and control */
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#define PLUM_VIDEO_POCKC_REG 0x018
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/* PLL Clock Source select and control */
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#define PLUM_VIDEO_POPLL_REG 0x01c
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/*
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* LCD Panel Control Register
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*/
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/* LCD Control */
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#define PLUM_VIDEO_PLCNT_REG 0x040
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/* STN Control */
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#define PLUM_VIDEO_PLSTN_REG 0x044
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/* LCD Level control */
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#define PLUM_VIDEO_PLLEV_REG 0x048
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/* LCD Luminance control */
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#define PLUM_VIDEO_PLLUM_REG 0x04c
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/* DSTN Dither Pattern base address */
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#define PLUM_VIDEO_PLDPA_REG 0x050
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/* DSTN VRAM Offscreen buffer address */
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#define PLUM_VIDEO_PLOSA_REG 0x054
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/*
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* CRT Control Register
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*/
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/* DAC Control */
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#define PLUM_VIDEO_PCDAC_REG 0x060
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/* CRT Border Color */
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#define PLUM_VIDEO_PCBOC_REG 0x064
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/* Palette snoop */
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#define PLUM_VIDEO_PCSNP_REG 0x068
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/*
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* LCD Timing Register
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*/
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/* Horizontanl Total */
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#define PLUM_VIDEO_PLHT_REG 0x080
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/* Horizontal Display Start */
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#define PLUM_VIDEO_PLHDS_REG 0x084
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/* H-Sync Start/End */
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#define PLUM_VIDEO_PLHSEHSS_REG 0x088
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/* H-Blanking Start/End */
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#define PLUM_VIDEO_PLHBEHSS_REG 0x08c
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/* Horizontal # of pixel */
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#define PLUM_VIDEO_PLHPX_REG 0x090
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/* Vertical Total */
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#define PLUM_VIDEO_PLVT_REG 0x094
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/* Vertical Display Start */
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#define PLUM_VIDEO_PLVDS_REG 0x098
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/* V-Sync Start/End */
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#define PLUM_VIDEO_PLVSEVSS_REG 0x09c
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/* V-Blankng Start/End */
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#define PLUM_VIDEO_PLVBEVBS_REG 0x0a0
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/* Current Line # */
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#define PLUM_VIDEO_PLCLN_REG 0x0a8
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/* Interrupt Line # */
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#define PLUM_VIDEO_PLILN_REG 0x0ac
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/* Mode */
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#define PLUM_VIDEO_PLMOD_REG 0x0b0
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/* LCD controller test */
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#define PLUM_VIDEO_PLTST_REG 0x0bc
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/*
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* LCD Graphics Register
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*/
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/* Double Buffer Select */
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#define PLUM_VIDEO_PLBSL_REG 0x0c0
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/* Graphics Display Start Address */
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#define PLUM_VIDEO_PLDSA0_REG 0x0c4
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#define PLUM_VIDEO_PLDSA1_REG 0x0c8
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/* VRAM Pitch 1 */
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#define PLUM_VIDEO_PLPIT1_REG 0x0cc
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/* VRAM Pitch 2 */
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#define PLUM_VIDEO_PLPIT2_REG 0x0d0
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/* VRAM Offset */
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#define PLUM_VIDEO_PLOFS_REG 0x0d4
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/* VRAM Lower Screen Address offset */
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#define PLUM_VIDEO_PLLSA_REG 0x0d8
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/* Graphics Mode */
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#define PLUM_VIDEO_PLGMD_REG 0x0dc
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#define PLUM_VIDEO_PLGMD_MASK 0x3
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#define PLUM_VIDEO_PLGMD_DISABLE 0x0
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#define PLUM_VIDEO_PLGMD_8BPP 0x1
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#define PLUM_VIDEO_PLGMD_16BPP 0x2
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/*
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* CRT Timing Register
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*/
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/* notyet */
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/*
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* CRT Graphics Register
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*/
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/* notyet */
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