831 lines
21 KiB
C
831 lines
21 KiB
C
/* $NetBSD: it8368.c,v 1.8 2000/03/12 15:35:29 uch Exp $ */
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/*
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* Copyright (c) 1999, 2000, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#undef WINCE_DEFAULT_SETTING /* for debug */
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#undef IT8368DEBUG
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#include "opt_tx39_debug.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <dev/pcmcia/pcmciareg.h>
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#include <dev/pcmcia/pcmciavar.h>
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#include <dev/pcmcia/pcmciachip.h>
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#include <hpcmips/tx/tx39var.h>
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#include <hpcmips/tx/txcsbusvar.h>
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#include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */
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#include <hpcmips/dev/it8368var.h>
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#include <hpcmips/dev/it8368reg.h>
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#ifdef IT8368DEBUG
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int it8368debug = 1;
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#define DPRINTF(arg) if (it8368debug) printf arg;
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#define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg;
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#else
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#define DPRINTF(arg)
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#define DPRINTFN(n, arg)
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#endif
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int it8368e_match __P((struct device*, struct cfdata*, void*));
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void it8368e_attach __P((struct device*, struct device*, void*));
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int it8368_print __P((void*, const char*));
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int it8368_submatch __P((struct device*, struct cfdata*, void*));
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#define IT8368_LASTSTATE_PRESENT 0x0002
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#define IT8368_LASTSTATE_HALF 0x0001
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#define IT8368_LASTSTATE_EMPTY 0x0000
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struct it8368e_softc {
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struct device sc_dev;
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struct device *sc_pcmcia;
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tx_chipset_tag_t sc_tc;
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/* Register space */
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bus_space_tag_t sc_csregt;
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bus_space_handle_t sc_csregh;
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/* I/O, attribute space */
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bus_space_tag_t sc_csiot;
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bus_addr_t sc_csiobase;
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bus_size_t sc_csiosize;
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/*
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* XXX theses means attribute memory. not memory space.
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* memory space is 0x64000000.
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*/
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bus_space_tag_t sc_csmemt;
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bus_addr_t sc_csmembase;
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bus_size_t sc_csmemsize;
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/* Separate I/O and attribute space mode */
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int sc_fixattr;
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/* Card interrupt handler */
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int (*sc_card_fun) __P((void*));
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void *sc_card_arg;
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void *sc_card_ih;
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int sc_card_irq;
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/* Card status change */
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int sc_irq;
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void *sc_ih;
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int sc_laststate;
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};
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void it8368_init_socket __P((struct it8368e_softc*));
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void it8368_attach_socket __P((struct it8368e_softc*));
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int it8368_intr __P((void*));
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int it8368_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t,
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struct pcmcia_mem_handle*));
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void it8368_chip_mem_free __P((pcmcia_chipset_handle_t,
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struct pcmcia_mem_handle*));
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int it8368_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
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bus_size_t, struct pcmcia_mem_handle*,
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bus_addr_t*, int*));
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void it8368_chip_mem_unmap __P((pcmcia_chipset_handle_t, int));
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int it8368_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t,
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bus_size_t, bus_size_t,
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struct pcmcia_io_handle*));
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void it8368_chip_io_free __P((pcmcia_chipset_handle_t,
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struct pcmcia_io_handle*));
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int it8368_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
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bus_size_t, struct pcmcia_io_handle*,
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int*));
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void it8368_chip_io_unmap __P((pcmcia_chipset_handle_t, int));
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void it8368_chip_socket_enable __P((pcmcia_chipset_handle_t));
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void it8368_chip_socket_disable __P((pcmcia_chipset_handle_t));
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void *it8368_chip_intr_establish __P((pcmcia_chipset_handle_t,
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struct pcmcia_function*, int,
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int (*) (void*), void*));
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void it8368_chip_intr_disestablish __P((pcmcia_chipset_handle_t, void*));
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#ifdef IT8368DEBUG
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void it8368_dump __P((struct it8368e_softc*));
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#endif
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static struct pcmcia_chip_functions it8368_functions = {
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it8368_chip_mem_alloc,
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it8368_chip_mem_free,
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it8368_chip_mem_map,
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it8368_chip_mem_unmap,
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it8368_chip_io_alloc,
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it8368_chip_io_free,
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it8368_chip_io_map,
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it8368_chip_io_unmap,
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it8368_chip_intr_establish,
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it8368_chip_intr_disestablish,
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it8368_chip_socket_enable,
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it8368_chip_socket_disable
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};
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struct cfattach it8368e_ca = {
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sizeof(struct it8368e_softc), it8368e_match, it8368e_attach
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};
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/*
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* IT8368 configuration register is big-endian.
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*/
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__inline__ u_int16_t it8368_reg_read __P((bus_space_tag_t,
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bus_space_handle_t, int));
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__inline__ void it8368_reg_write __P((bus_space_tag_t,
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bus_space_handle_t, int,
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u_int16_t));
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#ifdef IT8368E_DESTRUCTIVE_CHECK
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int it8368e_id_check __P((void *));
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/*
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* IT8368E don't have identification method. this is destructive check.
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*/
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int
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it8368e_id_check(aux)
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void *aux;
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{
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struct cs_attach_args *ca = aux;
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tx_chipset_tag_t tc;
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bus_space_tag_t csregt;
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bus_space_handle_t csregh;
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u_int16_t oreg, reg;
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int match = 0;
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tc = ca->ca_tc;
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csregt = ca->ca_csreg.cstag;
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bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize,
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0, &csregh);
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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oreg = reg;
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bitdisp(reg);
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reg &= ~IT8368_CTRL_BYTESWAP;
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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if (reg & IT8368_CTRL_BYTESWAP)
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goto nomatch;
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reg |= IT8368_CTRL_BYTESWAP;
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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if (!(reg & IT8368_CTRL_BYTESWAP))
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goto nomatch;
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match = 1;
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nomatch:
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg);
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bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize);
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return (match);
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}
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#endif /* IT8368E_DESTRUCTIVE_CHECK */
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int
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it8368e_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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#ifdef IT8368E_DESTRUCTIVE_CHECK
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return (it8368e_id_check(aux));
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#else
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return (1);
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#endif
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}
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void
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it8368e_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct cs_attach_args *ca = aux;
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struct it8368e_softc *sc = (void*)self;
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tx_chipset_tag_t tc;
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bus_space_tag_t csregt;
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bus_space_handle_t csregh;
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u_int16_t reg;
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sc->sc_tc = tc = ca->ca_tc;
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sc->sc_csregt = csregt = ca->ca_csreg.cstag;
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bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize,
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0, &sc->sc_csregh);
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csregh = sc->sc_csregh;
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sc->sc_csiot = ca->ca_csio.cstag;
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sc->sc_csiobase = ca->ca_csio.csbase;
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sc->sc_csiosize = ca->ca_csio.cssize;
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#ifdef IT8368DEBUG
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printf("\n\t[Windows CE setting]\n");
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it8368_dump(sc); /* print WindowsCE setting */
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#endif
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/* LHA[14:13] <= HA[14:13] */
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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reg &= ~IT8368_CTRL_ADDRSEL;
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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/* Set all MFIO direction as LHA[23:13] output pins */
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reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG);
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reg |= IT8368_MFIODIR_MASK;
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it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg);
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/* Set all MFIO functions as LHA */
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reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG);
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reg &= ~IT8368_MFIOSEL_MASK;
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it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg);
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/* Disable MFIO interrupt */
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reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG);
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reg &= ~IT8368_MFIOPOSINTEN_MASK;
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it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg);
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reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG);
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reg &= ~IT8368_MFIONEGINTEN_MASK;
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it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg);
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/* Port direction */
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reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 |
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IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 |
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IT8368_PIN_BCRDRST;
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it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg);
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printf("\n");
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/*
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* Separate I/O and attribute memory region
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*/
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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reg |= IT8368_CTRL_FIXATTRIO;
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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if (IT8368_CTRL_FIXATTRIO &
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it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) {
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sc->sc_fixattr = 1;
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printf("%s: fix attr mode\n", sc->sc_dev.dv_xname);
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} else {
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sc->sc_fixattr = 0;
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printf("%s: legacy attr mode\n", sc->sc_dev.dv_xname);
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}
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sc->sc_csmemt = sc->sc_csiot;
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sc->sc_csiosize /= 2;
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sc->sc_csmemsize = sc->sc_csiosize;
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sc->sc_csmembase = sc->sc_csiosize;
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#ifdef IT8368DEBUG
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it8368_dump(sc);
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#endif
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/* Enable card and interrupt driving. */
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reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
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reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN);
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if (sc->sc_fixattr)
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reg |= IT8368_CTRL_FIXATTRIO;
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it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
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sc->sc_irq = ca->ca_irq1;
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sc->sc_card_irq = ca->ca_irq3;
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it8368_attach_socket(sc);
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}
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__inline__ u_int16_t
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it8368_reg_read(t, h, ofs)
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bus_space_tag_t t;
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bus_space_handle_t h;
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int ofs;
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{
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u_int16_t val;
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val = bus_space_read_2(t, h, ofs);
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return 0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00));
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}
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__inline__ void
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it8368_reg_write(t, h, ofs, v)
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bus_space_tag_t t;
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bus_space_handle_t h;
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int ofs;
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u_int16_t v;
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{
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u_int16_t val;
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val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00));
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bus_space_write_2(t, h, ofs, val);
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}
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int
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it8368_intr(arg)
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void *arg;
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{
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struct it8368e_softc *sc = arg;
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bus_space_tag_t csregt = sc->sc_csregt;
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bus_space_handle_t csregh = sc->sc_csregh;
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u_int16_t reg;
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reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG);
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if (reg & IT8368_PIN_BCRDRDY) {
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if (sc->sc_card_fun) {
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/* clear interrupt */
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it8368_reg_write(csregt, csregh,
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IT8368_GPIONEGINTSTAT_REG,
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IT8368_PIN_BCRDRDY);
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/* Dispatch card interrupt handler */
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(*sc->sc_card_fun)(sc->sc_card_arg);
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}
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} else if (reg & IT8368_PIN_CRDDET2) {
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG,
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IT8368_PIN_CRDDET2);
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printf("[CSC]\n");
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#ifdef IT8368DEBUG
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it8368_dump(sc);
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#endif
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it8368_chip_socket_disable(sc);
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} else {
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#ifdef IT8368DEBUG
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u_int16_t reg2;
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reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2);
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printf("unknown it8368 interrupt: ");
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bitdisp(reg2);
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG,
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reg);
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#endif
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}
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return 0;
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}
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int
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it8368_print(arg, pnp)
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void *arg;
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const char *pnp;
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{
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if (pnp)
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printf("pcmcia at %s", pnp);
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return UNCONF;
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}
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int
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it8368_submatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return ((*cf->cf_attach->ca_match)(parent, cf, aux));
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}
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void
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it8368_attach_socket(sc)
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struct it8368e_softc *sc;
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{
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struct pcmciabus_attach_args paa;
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paa.paa_busname = "pcmcia";
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paa.pct = (pcmcia_chipset_tag_t)&it8368_functions;
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paa.pch = (pcmcia_chipset_handle_t)sc;
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paa.iobase = 0; /* I don't use them */
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paa.iosize = 0;
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if ((sc->sc_pcmcia = config_found_sm((void*)sc, &paa, it8368_print,
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it8368_submatch))) {
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it8368_init_socket(sc);
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}
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}
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void
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it8368_init_socket(sc)
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struct it8368e_softc *sc;
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{
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bus_space_tag_t csregt = sc->sc_csregt;
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bus_space_handle_t csregh = sc->sc_csregh;
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u_int16_t reg;
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/*
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* set up the card to interrupt on card detect
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*/
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reg = IT8368_PIN_CRDDET2; /* CSC */
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/* enable negative edge */
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it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
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/* disable positive edge */
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it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0);
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sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq,
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IST_EDGE, IPL_BIO, it8368_intr, sc);
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if (sc->sc_ih == NULL) {
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printf("%s: can't establish interrupt\n",
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sc->sc_dev.dv_xname);
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return;
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}
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/*
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* if there's a card there, then attach it.
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*/
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reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG);
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if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) {
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sc->sc_laststate = IT8368_LASTSTATE_EMPTY;
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} else {
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pcmcia_card_attach(sc->sc_pcmcia);
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sc->sc_laststate = IT8368_LASTSTATE_PRESENT;
|
|
}
|
|
}
|
|
|
|
void *
|
|
it8368_chip_intr_establish(pch, pf, ipl, ih_fun, ih_arg)
|
|
pcmcia_chipset_handle_t pch;
|
|
struct pcmcia_function *pf;
|
|
int ipl;
|
|
int (*ih_fun) __P((void *));
|
|
void *ih_arg;
|
|
{
|
|
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
|
bus_space_tag_t csregt = sc->sc_csregt;
|
|
bus_space_handle_t csregh = sc->sc_csregh;
|
|
u_int16_t reg;
|
|
|
|
if (sc->sc_card_fun)
|
|
panic("it8368_chip_intr_establish: "
|
|
"duplicate card interrupt handler.");
|
|
|
|
sc->sc_card_fun = ih_fun;
|
|
sc->sc_card_arg = ih_arg;
|
|
|
|
sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq,
|
|
IST_EDGE, IPL_BIO, it8368_intr,
|
|
sc);
|
|
|
|
/* enable card interrupt */
|
|
reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG);
|
|
reg |= IT8368_PIN_BCRDRDY;
|
|
it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
|
|
|
|
return sc->sc_card_ih;
|
|
}
|
|
|
|
void
|
|
it8368_chip_intr_disestablish(pch, ih)
|
|
pcmcia_chipset_handle_t pch;
|
|
void *ih;
|
|
{
|
|
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
|
bus_space_tag_t csregt = sc->sc_csregt;
|
|
bus_space_handle_t csregh = sc->sc_csregh;
|
|
u_int16_t reg;
|
|
|
|
if (!sc->sc_card_fun)
|
|
panic("it8368_chip_intr_disestablish:"
|
|
"no handler established.");
|
|
assert(ih == sc->sc_card_ih);
|
|
|
|
sc->sc_card_fun = 0;
|
|
sc->sc_card_arg = 0;
|
|
|
|
/* disable card interrupt */
|
|
reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG);
|
|
reg &= ~IT8368_PIN_BCRDRDY;
|
|
it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
|
|
|
|
tx_intr_disestablish(sc->sc_tc, ih);
|
|
}
|
|
|
|
int
|
|
it8368_chip_mem_alloc(pch, size, pcmhp)
|
|
pcmcia_chipset_handle_t pch;
|
|
bus_size_t size;
|
|
struct pcmcia_mem_handle *pcmhp;
|
|
{
|
|
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
|
|
|
if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase,
|
|
sc->sc_csmembase + sc->sc_csmemsize, size,
|
|
size, 0, 0, 0, &pcmhp->memh)) {
|
|
DPRINTF(("it8368_chip_mem_alloc: failed\n"));
|
|
return 1;
|
|
}
|
|
|
|
if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */
|
|
pcmhp->memh -= sc->sc_csmembase;
|
|
|
|
pcmhp->memt = sc->sc_csmemt;
|
|
pcmhp->addr = pcmhp->memh;
|
|
pcmhp->size = size;
|
|
pcmhp->realsize = size;
|
|
|
|
DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n",
|
|
(unsigned)pcmhp->memh, (unsigned)size));
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
it8368_chip_mem_free(pch, pcmhp)
|
|
pcmcia_chipset_handle_t pch;
|
|
struct pcmcia_mem_handle *pcmhp;
|
|
{
|
|
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
|
|
|
DPRINTF(("it8368_chip_mem_free: %#x+%#x\n",
|
|
(unsigned)pcmhp->memh, (unsigned)pcmhp->size));
|
|
|
|
if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */
|
|
pcmhp->memh += sc->sc_csmembase;
|
|
|
|
bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size);
|
|
}
|
|
|
|
int
|
|
it8368_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp)
|
|
pcmcia_chipset_handle_t pch;
|
|
int kind;
|
|
bus_addr_t card_addr;
|
|
bus_size_t size;
|
|
struct pcmcia_mem_handle *pcmhp;
|
|
bus_addr_t *offsetp;
|
|
int *windowp;
|
|
{
|
|
/* attribute mode */
|
|
it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16);
|
|
|
|
*offsetp = card_addr;
|
|
DPRINTF(("it8368_chip_mem_map %#x+%#x\n",
|
|
(unsigned)pcmhp->memh, (unsigned)size));
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
it8368_chip_mem_unmap(pch, window)
|
|
pcmcia_chipset_handle_t pch;
|
|
int window;
|
|
{
|
|
/* return to I/O mode */
|
|
it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16);
|
|
}
|
|
|
|
void
|
|
it8368_mode(pch, io, width)
|
|
pcmcia_chipset_handle_t pch;
|
|
int io;
|
|
int width;
|
|
{
|
|
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
|
txreg_t reg32;
|
|
|
|
DPRINTF(("it8368_mode: change access space to "));
|
|
DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n",
|
|
width == IT8368_WIDTH_8 ? 8 : 16));
|
|
|
|
reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
|
|
|
|
if (io) {
|
|
if (width == IT8368_WIDTH_8)
|
|
reg32 |= TX39_MEMCONFIG3_PORT8SEL;
|
|
else
|
|
reg32 &= ~TX39_MEMCONFIG3_PORT8SEL;
|
|
}
|
|
|
|
if (!sc->sc_fixattr) {
|
|
if (io)
|
|
reg32 |= TX39_MEMCONFIG3_CARD1IOEN;
|
|
else
|
|
reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN;
|
|
}
|
|
tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32);
|
|
|
|
#ifdef IT8368DEBUG
|
|
if (sc->sc_fixattr)
|
|
return; /* No need to report BIU status */
|
|
|
|
/* check BIU status */
|
|
reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
|
|
if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) {
|
|
DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n",
|
|
reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16));
|
|
} else {
|
|
DPRINTF(("it8368_mode: atttribute space enabled\n"));
|
|
}
|
|
#endif /* IT8368DEBUG */
|
|
}
|
|
|
|
int
|
|
it8368_chip_io_alloc(pch, start, size, align, pcihp)
|
|
pcmcia_chipset_handle_t pch;
|
|
bus_addr_t start;
|
|
bus_size_t size;
|
|
bus_size_t align;
|
|
struct pcmcia_io_handle *pcihp;
|
|
{
|
|
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
|
|
|
if (start) {
|
|
if (bus_space_map(sc->sc_csiot, start, size, 0,
|
|
&pcihp->ioh)) {
|
|
return 1;
|
|
}
|
|
DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n",
|
|
(unsigned)start, (unsigned)size));
|
|
} else {
|
|
if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase,
|
|
sc->sc_csiobase + sc->sc_csiosize,
|
|
size, align, 0, 0, &pcihp->addr,
|
|
&pcihp->ioh)) {
|
|
|
|
return 1;
|
|
}
|
|
pcihp->flags = PCMCIA_IO_ALLOCATED;
|
|
DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n",
|
|
(unsigned)size, (unsigned)pcihp->addr));
|
|
}
|
|
|
|
pcihp->iot = sc->sc_csiot;
|
|
pcihp->size = size;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
it8368_chip_io_map(pch, width, offset, size, pcihp, windowp)
|
|
pcmcia_chipset_handle_t pch;
|
|
int width;
|
|
bus_addr_t offset;
|
|
bus_size_t size;
|
|
struct pcmcia_io_handle *pcihp;
|
|
int *windowp;
|
|
{
|
|
/* I/O mode */
|
|
it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16);
|
|
|
|
DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n",
|
|
(unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size));
|
|
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
it8368_chip_io_free(pch, pcihp)
|
|
pcmcia_chipset_handle_t pch;
|
|
struct pcmcia_io_handle *pcihp;
|
|
{
|
|
if (pcihp->flags & PCMCIA_IO_ALLOCATED)
|
|
bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size);
|
|
else
|
|
bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size);
|
|
|
|
DPRINTF(("it8368_chip_io_free %#x+%#x\n",
|
|
(unsigned)pcihp->ioh, (unsigned)pcihp->size));
|
|
}
|
|
|
|
void
|
|
it8368_chip_io_unmap(pch, window)
|
|
pcmcia_chipset_handle_t pch;
|
|
int window;
|
|
{
|
|
}
|
|
|
|
void
|
|
it8368_chip_socket_enable(pch)
|
|
pcmcia_chipset_handle_t pch;
|
|
{
|
|
#ifndef WINCE_DEFAULT_SETTING
|
|
struct it8368e_softc *sc = (struct it8368e_softc*)pch;
|
|
bus_space_tag_t csregt = sc->sc_csregt;
|
|
bus_space_handle_t csregh = sc->sc_csregh;
|
|
volatile u_int16_t reg;
|
|
|
|
/* Power off */
|
|
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
|
reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
|
|
reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V);
|
|
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
|
delay(20000);
|
|
|
|
/*
|
|
* wait 300ms until power fails (Tpf). Then, wait 100ms since
|
|
* we are changing Vcc (Toff).
|
|
*/
|
|
delay((300 + 100) * 1000);
|
|
|
|
/* Supply Vcc */
|
|
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
|
reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
|
|
reg |= IT8368_PIN_CRDVCC_5V; /* XXX */
|
|
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
|
|
|
/*
|
|
* wait 100ms until power raise (Tpr) and 20ms to become
|
|
* stable (Tsu(Vcc)).
|
|
*
|
|
* some machines require some more time to be settled
|
|
* (300ms is added here).
|
|
*/
|
|
delay((100 + 20 + 300) * 1000);
|
|
|
|
/* Assert reset signal */
|
|
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
|
reg |= IT8368_PIN_BCRDRST;
|
|
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
|
|
|
/*
|
|
* hold RESET at least 10us.
|
|
*/
|
|
delay(10);
|
|
|
|
/* deassert reset signal */
|
|
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
|
reg &= ~IT8368_PIN_BCRDRST;
|
|
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
|
delay(20000);
|
|
|
|
DPRINTF(("it8368_chip_socket_enable: socket enabled\n"));
|
|
#endif /* !WINCE_DEFAULT_SETTING */
|
|
}
|
|
|
|
void
|
|
it8368_chip_socket_disable(pch)
|
|
pcmcia_chipset_handle_t pch;
|
|
{
|
|
#ifndef WINCE_DEFAULT_SETTING
|
|
struct it8368e_softc *sc = (struct it8368e_softc*) pch;
|
|
bus_space_tag_t csregt = sc->sc_csregt;
|
|
bus_space_handle_t csregh = sc->sc_csregh;
|
|
u_int16_t reg;
|
|
|
|
/* Power down */
|
|
reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
|
|
reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
|
|
reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V);
|
|
it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
|
|
delay(20000);
|
|
|
|
/*
|
|
* wait 300ms until power fails (Tpf).
|
|
*/
|
|
delay(300 * 1000);
|
|
|
|
DPRINTF(("it8368_chip_socket_disable: socket disabled\n"));
|
|
#endif /* !WINCE_DEFAULT_SETTING */
|
|
}
|
|
|
|
#ifdef IT8368DEBUG
|
|
#define PRINTGPIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \
|
|
IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, 1)
|
|
#define PRINTMFIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \
|
|
IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, 1)
|
|
void
|
|
it8368_dump(sc)
|
|
struct it8368e_softc *sc;
|
|
{
|
|
bus_space_tag_t csregt = sc->sc_csregt;
|
|
bus_space_handle_t csregh = sc->sc_csregh;
|
|
|
|
printf("[GPIO]\n");
|
|
PRINTGPIO(DIR);
|
|
PRINTGPIO(DATAIN);
|
|
PRINTGPIO(DATAOUT);
|
|
PRINTGPIO(POSINTEN);
|
|
PRINTGPIO(NEGINTEN);
|
|
PRINTGPIO(POSINTSTAT);
|
|
PRINTGPIO(NEGINTSTAT);
|
|
printf("[MFIO]\n");
|
|
PRINTMFIO(SEL);
|
|
PRINTMFIO(DIR);
|
|
PRINTMFIO(DATAIN);
|
|
PRINTMFIO(DATAOUT);
|
|
PRINTMFIO(POSINTEN);
|
|
PRINTMFIO(NEGINTEN);
|
|
PRINTMFIO(POSINTSTAT);
|
|
PRINTMFIO(NEGINTSTAT);
|
|
__bitdisp(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15,
|
|
"CTRL", 1);
|
|
__bitdisp(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG),
|
|
8, 11, "]CRDDET/SENSE[", 1);
|
|
}
|
|
#endif /* IT8368DEBUG */
|