390 lines
11 KiB
C
390 lines
11 KiB
C
/* $Id: imxuartreg.h,v 1.2 2008/04/27 18:58:44 matt Exp $ */
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/*
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* register definitions for Freescale i.MX31 and i.MX31L UARTs
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*
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* UART specification obtained from:
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* MCIMX31 and MCIMX31L Application Processors
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* Reference Manual
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* MCIMC31RM
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* Rev. 2.3
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* 1/2007
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*/
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/*
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* Registers are 32 bits wide; the 16 MSBs are unused --
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* they read as zeros and are ignored on write.
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*/
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#define BITS(hi,lo) ((uint32_t)(~((~0ULL)<<((hi)+1)))&((~0)<<(lo)))
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#define BIT(n) ((uint32_t)(1 << (n)))
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/*
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* register base addrs
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*/
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#define IMX_UART1_BASE 0x43f90000
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#define IMX_UART2_BASE 0x43f94000
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#define IMX_UART3_BASE 0x5000C000
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#define IMX_UART4_BASE 0x43fb0000
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#define IMX_UART5_BASE 0x43fb4000
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/*
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* register offsets
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*/
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#define IMX_URXD 0x00 /* r */ /* UART Receiver Reg */
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#define IMX_UTXD 0x40 /* w */ /* UART Transmitter Reg */
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#define IMX_UCR1 0x80 /* rw */ /* UART Control Reg 1 */
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#define IMX_UCR2 0x84 /* rw */ /* UART Control Reg 2 */
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#define IMX_UCR3 0x88 /* rw */ /* UART Control Reg 3 */
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#define IMX_UCR4 0x8c /* rw */ /* UART Control Reg 4 */
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#define IMX_UCRn(n) (IMX_UCR1 + ((n) << 2))
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#define IMX_UFCR 0x90 /* rw */ /* UART FIFO Control Reg */
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#define IMX_USR1 0x94 /* rw */ /* UART Status Reg 1 */
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#define IMX_USR2 0x98 /* rw */ /* UART Status Reg 2 */
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#define IMX_USRn(n) (IMX_USR1 + ((n) << 2))
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#define IMX_UESC 0x9c /* rw */ /* UART Escape Character Reg */
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#define IMX_UTIM 0xa0 /* rw */ /* UART Escape Timer Reg */
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#define IMX_UBIR 0xa4 /* rw */ /* UART BRM Incremental Reg */
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#define IMX_UBMR 0xa8 /* rw */ /* UART BRM Modulator Reg */
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#define IMX_UBRC 0xac /* r */ /* UART Baud Rate Count Reg */
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#define IMX_ONEMS 0xb0 /* rw */ /* UART One Millisecond Reg */
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#define IMX_UTS 0xb4 /* rw */ /* UART Test Reg */
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/*
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* bit attributes:
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* ro read-only
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* wo write-only
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* rw read/write
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* w1c write 1 to clear
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*
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* attrs defined but apparently unused for the UART:
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* rwm rw bit that can be modified by HW (other than reset)
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* scb self-clear: write 1 has some effect, always reads as 0
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*/
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/*
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* IMX_URXD bits
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*/
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#define IMX_URXD_RX_DATA BITS(7,0) /* ro */
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#define IMX_URXD_RESV BITS(9,8) /* ro */
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#define IMX_URXD_PRERR BIT(10) /* ro */
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#define IMX_URXD_BRK BIT(11) /* ro */
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#define IMX_URXD_FRMERR BIT(12) /* ro */
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#define IMX_URXD_OVRRUN BIT(13) /* ro */
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#define IMX_URXD_ERR BIT(14) /* ro */
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#define IMX_URXD_CHARDY BIT(15) /* ro */
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/*
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* IMX_UTXD bits
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*/
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#define IMX_UTXD_TX_DATA BITS(7,0) /* wo */
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#define IMX_UTXD_RESV BITS(15,8)
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/*
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* IMX_UCR1 bits
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*/
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#define IMX_UCR1_UARTEN BIT(0) /* rw */
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#define IMX_UCR1_DOZE BIT(1) /* rw */
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#define IMX_UCR1_ATDMAEN BIT(2) /* rw */
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#define IMX_UCR1_TXDMAEN BIT(3) /* rw */
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#define IMX_UCR1_SNDBRK BIT(4) /* rw */
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#define IMX_UCR1_RTSDEN BIT(5) /* rw */
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#define IMX_UCR1_TXMPTYEN BIT(6) /* rw */
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#define IMX_UCR1_IREN BIT(7) /* rw */
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#define IMX_UCR1_RXDMAEN BIT(8) /* rw */
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#define IMX_UCR1_RRDYEN BIT(9) /* rw */
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#define IMX_UCR1_ICD BITS(11,10) /* rw */
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#define IMX_UCR1_IDEN BIT(12) /* rw */
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#define IMX_UCR1_TRDYEN BIT(13) /* rw */
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#define IMX_UCR1_ADBR BIT(14) /* rw */
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#define IMX_UCR1_ADEN BIT(15) /* rw */
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/*
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* IMX_UCR2 bits
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*/
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#define IMX_UCR2_SRST BIT(0) /* rw */
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#define IMX_UCR2_RXEN BIT(1) /* rw */
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#define IMX_UCR2_TXEN BIT(2) /* rw */
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#define IMX_UCR2_ATEN BIT(3) /* rw */
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#define IMX_UCR2_RTSEN BIT(4) /* rw */
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#define IMX_UCR2_WS BIT(5) /* rw */
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#define IMX_UCR2_STPB BIT(6) /* rw */
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#define IMX_UCR2_PRDE BIT(7) /* rw */
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#define IMX_UCR2_PREN BIT(8) /* rw */
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#define IMX_UCR2_RTEC BITS(10,9) /* rw */
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#define IMX_UCR2_ESCEN BIT(11) /* rw */
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#define IMX_UCR2_CTS BIT(12) /* rw */
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#define IMX_UCR2_CTSC BIT(13) /* rw */
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#define IMX_UCR2_IRTS BIT(14) /* rw */
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#define IMX_UCR2_ESCI BIT(15) /* rw */
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/*
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* IMX_UCR3 bits
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*/
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#define IMX_UCR3_ACIEN BIT(0) /* rw */
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#define IMX_UCR3_INVT BIT(1) /* rw */
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#define IMX_UCR3_RXDMUXSEL BIT(2) /* rw */
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#define IMX_UCR3_DTRDEN BIT(3) /* rw */
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#define IMX_UCR3_AWAKEN BIT(4) /* rw */
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#define IMX_UCR3_AIRINTEN BIT(5) /* rw */
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#define IMX_UCR3_RXDSEN BIT(6) /* rw */
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#define IMX_UCR3_ADNIMP BIT(7) /* rw */
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#define IMX_UCR3_RI BIT(8) /* rw */
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#define IMX_UCR3_DCD BIT(9) /* rw */
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#define IMX_UCR3_DSR BIT(10) /* rw */
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#define IMX_UCR3_FRAERREN BIT(11) /* rw */
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#define IMX_UCR3_PARERREN BIT(12) /* rw */
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#define IMX_UCR3_DTREN BIT(13) /* rw */
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#define IMX_UCR3_DPEC BITS(15,14) /* rw */
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/*
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* IMX_UCR4 bits
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*/
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#define IMX_UCR4_DREN BIT(0) /* rw */
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#define IMX_UCR4_OREN BIT(1) /* rw */
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#define IMX_UCR4_BKEN BIT(2) /* rw */
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#define IMX_UCR4_TCEN BIT(3) /* rw */
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#define IMX_UCR4_LPBYP BIT(4) /* rw */
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#define IMX_UCR4_IRSC BIT(5) /* rw */
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#define IMX_UCR4_IDDMAEN BIT(6) /* rw */
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#define IMX_UCR4_WKEN BIT(7) /* rw */
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#define IMX_UCR4_ENIRI BIT(8) /* rw */
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#define IMX_UCR4_INVR BIT(9) /* rw */
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#define IMX_UCR4_CTSTL BITS(15,10) /* rw */
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/*
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* IMX_UFCR bits
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*/
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#define IMX_UFCR_RXTL BITS(5,0) /* rw */
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#define IMX_UFCR_DCEDTE BIT(6) /* rw */
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#define IMX_UFCR_RFDIV BITS(9,7) /* rw */
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#define IMX_UFCR_TXTL BITS(15,8) /* rw */
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/*
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* IMX_USR1 bits
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*/
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#define IMX_USR1_RESV BITS(3,0)
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#define IMX_USR1_AWAKE BIT(4) /* w1c */
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#define IMX_USR1_AIRINT BIT(5) /* w1c */
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#define IMX_USR1_RXDS BIT(6) /* ro */
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#define IMX_USR1_DTRD BIT(7) /* w1c */
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#define IMX_USR1_AGTIM BIT(8) /* w1c */
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#define IMX_USR1_RRDY BIT(9) /* ro */
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#define IMX_USR1_FRAMERR BIT(10) /* w1c */
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#define IMX_USR1_ESCF BIT(11) /* w1c */
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#define IMX_USR1_RTSD BIT(12) /* w1c */
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#define IMX_USR1_TRDY BIT(13) /* ro */
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#define IMX_USR1_RTSS BIT(14) /* ro */
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#define IMX_USR1_PARITYERR BIT(15) /* w1c */
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/*
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* IMX_USR2 bits
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*/
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#define IMX_USR2_RDR BIT(0)
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#define IMX_USR2_ORE BIT(1) /* w1c */
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#define IMX_USR2_BRCD BIT(2) /* w1c */
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#define IMX_USR2_TXDC BIT(3) /* ro */
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#define IMX_USR2_RTSF BIT(4) /* w1c */
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#define IMX_USR2_DCDIN BIT(5) /* ro */
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#define IMX_USR2_DCDDELT BIT(6) /* rw */
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#define IMX_USR2_WAKE BIT(7) /* w1c */
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#define IMX_USR2_IRINT BIT(8) /* rw */
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#define IMX_USR2_RIIN BIT(9) /* ro */
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#define IMX_USR2_RIDELT BIT(10) /* w1c */
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#define IMX_USR2_ACST BIT(11) /* rw */
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#define IMX_USR2_IDLE BIT(12) /* w1c */
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#define IMX_USR2_DTRF BIT(13) /* rw */
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#define IMX_USR2_TXFE BIT(14) /* ro */
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#define IMX_USR2_ADET BIT(15) /* w1c */
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/*
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* IMX_UESC bits
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*/
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#define IMX_UESC_ESC_CHAR BITS(7,0) /* rw */
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#define IMX_UESC_RESV BITS(15,8)
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/*
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* IMX_UTIM bits
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*/
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#define IMX_UTIM_TIM BITS(11,0) /* rw */
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#define IMX_UTIM_RESV BITS(15,12)
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/*
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* IMX_UBIR bits
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*/
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#define IMX_UBIR_INC BITS(15,0) /* rw */
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/*
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* IMX_UBMR bits
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*/
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#define IMX_UBMR_MOD BITS(15,0) /* rw */
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/*
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* IMX_UBRC bits
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*/
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#define IMX_UBRC_BCNT BITS(15,0) /* ro */
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/*
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* IMX_ONEMS bits
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*/
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#define IMX_ONEMS_ONEMS BITS(15,0) /* rw */
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/*
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* IMX_UTS bits
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*/
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#define IMX_UTS_SOFTRST BIT(0) /* rw */
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#define IMX_UTS_RESVa BITS(2,1)
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#define IMX_UTS_RXFULL BIT(3) /* rw */
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#define IMX_UTS_TXFUL BIT(4) /* rw */
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#define IMX_UTS_RXEMPTY BIT(5) /* rw */
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#define IMX_UTS_TXEMPTY BIT(5) /* rw */
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#define IMX_UTS_RESVb BITS(8,7)
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#define IMX_UTS_RXDBG BIT(9) /* rw */
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#define IMX_UTS_LOOPIR BIT(10) /* rw */
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#define IMX_UTS_DBGEN BIT(11) /* rw */
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#define IMX_UTS_LOOP BIT(12) /* rw */
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#define IMX_UTS_FRCPERR BIT(13) /* rw */
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#define IMX_UTS_RESVc BITS(15,14)
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#define IMX_UTS_RESV (IMX_UTS_RESVa|IMX_UTS_RESVb|IMX_UTS_RESVc)
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/*
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* interrupt specs
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* see Table 31-25. "Interrupts an DMA"
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*/
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/*
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* abstract interrupts spec indexing
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*/
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typedef enum {
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RX_RRDY=0,
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RX_ID,
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RX_DR,
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RX_RXDS,
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RX_AT,
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TX_TXMPTY,
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TX_TRDY,
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TX_TC,
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MINT_OR,
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MINT_BR,
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MINT_WK,
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MINT_AD,
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MINT_ACI,
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MINT_ESCI,
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MINT_IRI,
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MINT_AIRINT,
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MINT_AWAK,
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MINT_FRAERR,
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MINT_PARERR,
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MINT_RTSD,
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MINT_RTS,
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MINT_DCE_DTR,
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MINT_DTE_RI,
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MINT_DTE_DCE,
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MINT_DTRD,
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RX_DMAREQ_RXDMA,
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RX_DMAREQ_ATDMA,
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RX_DMAREQ_IDDMA,
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RX_DMAREQ_TXDMA,
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} imxuart_intrix_t;
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/*
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* abstract interrupts spec
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*/
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typedef struct {
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const uint32_t enb_bit;
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const uint enb_reg;
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const uint32_t flg_bit;
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const uint flg_reg;
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const char * name; /* for debug */
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} imxuart_intrspec_t;
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#define IMXUART_INTRSPEC(cv, cr, sv, sr) \
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{ IMX_UCR##cr##_##cv, ((cr) - 1), IMX_USR##sr##_##sv, ((sr) - 1), #sv }
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static const imxuart_intrspec_t imxuart_intrspec_tab[] = {
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/* ipi_uart_rx */
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IMXUART_INTRSPEC(RRDYEN, 1, RRDY, 1),
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IMXUART_INTRSPEC(IDEN, 1, IDLE, 2),
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IMXUART_INTRSPEC(DREN, 4, RDR, 2),
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IMXUART_INTRSPEC(RXDSEN, 3, RXDS, 1),
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IMXUART_INTRSPEC(ATEN, 2, AGTIM, 1),
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/* ipi_uart_tx */
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IMXUART_INTRSPEC(TXMPTYEN, 1, TXFE, 2),
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IMXUART_INTRSPEC(TRDYEN, 1, TRDY, 1),
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IMXUART_INTRSPEC(TCEN, 4, TXDC, 2),
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/* ipi_uart_mint */
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IMXUART_INTRSPEC(OREN, 4, ORE, 2),
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IMXUART_INTRSPEC(BKEN, 4, BRCD, 2),
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IMXUART_INTRSPEC(WKEN, 4, WAKE, 2),
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IMXUART_INTRSPEC(ADEN, 1, ADET, 2),
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IMXUART_INTRSPEC(ACIEN, 3, ACST, 2),
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IMXUART_INTRSPEC(ESCI, 2, ESCF, 1),
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IMXUART_INTRSPEC(ENIRI, 4, IRINT, 2),
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IMXUART_INTRSPEC(AIRINTEN, 3, AIRINT, 1),
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IMXUART_INTRSPEC(AWAKEN, 3, AWAKE, 1),
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IMXUART_INTRSPEC(FRAERREN, 3, FRAMERR, 1),
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IMXUART_INTRSPEC(PARERREN, 3, PARITYERR, 1),
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IMXUART_INTRSPEC(RTSDEN, 1, RTSD, 1),
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IMXUART_INTRSPEC(RTSEN, 2, RTSF, 2),
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IMXUART_INTRSPEC(DTREN, 3, DTRF, 2),
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IMXUART_INTRSPEC(RI, 3, DTRF, 2),
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IMXUART_INTRSPEC(DCD, 3, DCDDELT, 2),
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IMXUART_INTRSPEC(DTRDEN, 3, DTRD, 1),
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/* ipd_uart_rx_dmareq */
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IMXUART_INTRSPEC(RXDMAEN, 1, RRDY, 1),
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IMXUART_INTRSPEC(ATDMAEN, 1, AGTIM, 1),
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IMXUART_INTRSPEC(IDDMAEN, 4, IDLE, 2),
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/* ipd_uart_tx_dmareq */
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IMXUART_INTRSPEC(TXDMAEN, 1, TRDY, 1),
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};
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#define IMXUART_INTRSPEC_TAB_SZ \
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(sizeof(imxuart_intrspec_tab) / sizeof(imxuart_intrspec_tab[0]))
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/*
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* functional groupings of intr status flags by reg
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*/
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#define IMXUART_RXINTR_USR1 (IMX_USR1_RRDY|IMX_USR1_RXDS|IMX_USR1_AGTIM)
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#define IMXUART_RXINTR_USR2 (IMX_USR2_IDLE|IMX_USR2_RDR)
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#define IMXUART_TXINTR_USR1 (IMX_USR1_TRDY)
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#define IMXUART_TXINTR_USR2 (IMX_USR2_TXFE|IMX_USR2_TXDC)
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#define IMXUART_MINT_USR1 (IMX_USR1_ESCF|IMX_USR1_AIRINT||IMX_USR1_AWAKE \
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|IMX_USR1_FRAMERR|IMX_USR1_PARITYERR \
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|IMX_USR1_RTSD|IMX_USR1_DTRD)
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#define IMXUART_MINT_USR2 (IMX_USR2_ORE|IMX_USR2_BRCD|IMX_USR2_WAKE \
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|IMX_USR2_ADET|IMX_USR2_ACST|IMX_USR2_IRINT \
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|IMX_USR2_RTSF|IMX_USR2_DTRF|IMX_USR2_DTRF \
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|IMX_USR2_DCDDELT)
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#define IMXUART_RXDMA_USR1 (IMX_USR1_RRDY|IMX_USR1_AGTIM)
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#define IMXUART_RXDMA_USR2 (IMX_USR2_IDLE)
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#define IMXUART_TXDMA_USR1 (IMX_USR1_TRDY)
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#define IMXUART_TXDMA_USR2 (0)
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/*
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* all intr status flags by reg
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*/
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#define IMXUART_INTRS_USR1 (IMXUART_RXINTR_USR1|IMXUART_TXINTR_USR1 \
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|IMXUART_MINT_USR1|IMXUART_RXDMA_USR1 \
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|IMXUART_TXDMA_USR1)
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#define IMXUART_INTRS_USR2 (IMXUART_RXINTR_USR2|IMXUART_TXINTR_USR2 \
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|IMXUART_MINT_USR2|IMXUART_RXDMA_USR2 \
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|IMXUART_TXDMA_USR2)
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/*
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* all intr controls by reg
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*/
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#define IMXUART_INTRS_UCR1 (IMX_UCR1_RRDYEN|IMX_UCR1_IDEN \
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|IMX_UCR1_TXMPTYEN|IMX_UCR1_TRDYEN \
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|IMX_UCR1_ADEN|IMX_UCR1_RTSDEN \
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|IMX_UCR1_RXDMAEN|IMX_UCR1_RXDMAEN \
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|IMX_UCR1_ATDMAEN|IMX_UCR1_TXDMAEN)
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#define IMXUART_INTRS_UCR2 (IMX_UCR2_ATEN|IMX_UCR2_ESCI|IMX_UCR2_RTSEN)
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#define IMXUART_INTRS_UCR3 (IMX_UCR3_RXDSEN|IMX_UCR3_ACIEN \
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|IMX_UCR3_AIRINTEN|IMX_UCR3_AWAKEN \
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|IMX_UCR3_FRAERREN|IMX_UCR3_PARERREN \
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|IMX_UCR3_DTREN|IMX_UCR3_RI \
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|IMX_UCR3_DCD|IMX_UCR3_DTRDEN)
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#define IMXUART_INTRS_UCR4 (IMX_UCR4_DREN|IMX_UCR4_TCEN|IMX_UCR4_OREN \
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|IMX_UCR4_BKEN|IMX_UCR4_WKEN \
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|IMX_UCR4_ENIRI|IMX_UCR4_IDDMAEN)
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