293 lines
7.8 KiB
C
293 lines
7.8 KiB
C
/* $NetBSD: pte.h,v 1.5 1997/06/21 04:10:42 mhitch Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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#ifndef __MIPS_PTE_H__
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#define __MIPS_PTE_H__
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#include <mips/mips1_pte.h>
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#include <mips/mips3_pte.h>
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#if !defined(MIPS1) && !defined(MIPS3)
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#error Must include at least one MIPS architecture.
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#endif
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#define PG_ASID 0x000000ff /* Address space ID */
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#ifndef _LOCORE
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#include <mips/cpu.h>
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typedef union pt_entry {
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unsigned int pt_entry; /* for copying, etc. */
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struct mips1_pte pt_mips1_pte; /* for getting to bits by name */
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struct mips3_pte pt_mips3_pte;
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} pt_entry_t;
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#define PT_ENTRY_NULL ((pt_entry_t *) 0)
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/*
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* Macros/inline functions to hide PTE format differences.
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*/
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#define mips_pg_nv_bit() (MIPS1_PG_NV) /* same on mips1 and mips3 */
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int pmap_is_page_ro(pmap_t, vm_offset_t, int);
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/* MIPS1-only */
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#if defined(MIPS1) && !defined(MIPS3)
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#define mips_pg_v(entry) ((entry) & MIPS1_PG_V)
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#define mips_pg_wired(entry) ((entry) & MIPS1_PG_WIRED)
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#define mips_pg_m_bit() (MIPS1_PG_M)
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#define mips_pg_rw_bit() (MIPS1_PG_RW) /* no RW bits for mips1 */
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#define mips_pg_ro_bit() (MIPS1_PG_RO)
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#define mips_pg_ropage_bit() (MIPS1_PG_RO) /* XXX not MIPS1_PG_ROPAGE? */
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#define mips_pg_rwpage_bit() (MIPS1_PG_RWPAGE)
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#define mips_pg_cwpage_bit() (MIPS1_PG_CWPAGE)
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#define mips_pg_global_bit() (MIPS1_PG_G)
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#define mips_pg_wired_bit() (MIPS1_PG_WIRED)
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#define PTE_TO_PADDR(pte) MIPS1_PTE_TO_PADDR((pte))
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#define PAGE_IS_RDONLY(pte, va) MIPS1_PAGE_IS_RDONLY((pte), (va))
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#define pfn_to_vad(x) mips1_pfn_to_vad((vm_offset_t)(x))
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#define vad_to_pfn(x) mips1_vad_to_pfn((x))
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#endif /* mips1 */
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/* MIPS3-only */
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#if !defined(MIPS1) && defined(MIPS3)
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#define mips_pg_v(entry) ((entry) & MIPS3_PG_V)
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#define mips_pg_wired(entry) ((entry) & MIPS3_PG_WIRED)
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#define mips_pg_m_bit() (MIPS3_PG_M)
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#define mips_pg_rw_bit() (MIPS3_PG_M)
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#define mips_pg_ro_bit() (MIPS3_PG_RO)
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#define mips_pg_ropage_bit() (MIPS3_PG_ROPAGE)
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#define mips_pg_rwpage_bit() (MIPS3_PG_RWPAGE)
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#define mips_pg_cwpage_bit() (MIPS3_PG_CWPAGE)
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#define mips_pg_global_bit() (MIPS3_PG_G)
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#define mips_pg_wired_bit() (MIPS3_PG_WIRED)
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#define PTE_TO_PADDR(pte) MIPS3_PTE_TO_PADDR((pte))
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#define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va))
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#define pfn_to_vad(x) mips3_pfn_to_vad((vm_offset_t)(x))
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#define vad_to_pfn(x) mips3_vad_to_pfn((x))
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#endif /* mips3 */
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/* MIPS1 and MIPS3 */
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#if defined(MIPS1) && defined(MIPS3)
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static __inline int
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mips_pg_v(unsigned int entry),
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mips_pg_wired(unsigned int entry),
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PAGE_IS_RDONLY(unsigned int pte, vm_offset_t va);
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static __inline unsigned int
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mips_pg_wired_bit(void), mips_pg_m_bit(void),
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mips_pg_ro_bit(void), mips_pg_rw_bit(void),
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mips_pg_ropage_bit(void),
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mips_pg_cwpage_bit(void),
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mips_pg_rwpage_bit(void),
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mips_pg_global_bit(void),
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PTE_TO_PADDR(unsigned int entry);
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static __inline vm_offset_t pfn_to_vad(unsigned int x);
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static __inline int vad_to_pfn(vm_offset_t x);
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static __inline int
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mips_pg_v(entry)
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unsigned int entry;
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{
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if (CPUISMIPS3)
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return (entry & MIPS3_PG_V);
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return (entry & MIPS1_PG_V);
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}
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static __inline int
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mips_pg_wired(entry)
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unsigned int entry;
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{
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if (CPUISMIPS3)
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return (entry & MIPS3_PG_WIRED);
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return (entry & MIPS1_PG_WIRED);
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}
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static __inline unsigned int
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mips_pg_m_bit()
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{
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if (CPUISMIPS3)
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return (MIPS3_PG_M);
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return (MIPS1_PG_M);
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}
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static __inline unsigned int
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mips_pg_ro_bit()
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{
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if (CPUISMIPS3)
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return (MIPS3_PG_RO);
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return (MIPS1_PG_RO);
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}
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static __inline unsigned int
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mips_pg_rw_bit()
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{
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if (CPUISMIPS3)
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return (MIPS3_PG_M);
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return (MIPS1_PG_RW);
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}
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static __inline unsigned int
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mips_pg_ropage_bit()
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{
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if (CPUISMIPS3)
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return (MIPS3_PG_ROPAGE);
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return (MIPS1_PG_RO);
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}
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static __inline unsigned int
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mips_pg_rwpage_bit()
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{
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if (CPUISMIPS3)
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return (MIPS3_PG_RWPAGE);
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return (MIPS1_PG_RWPAGE);
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}
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static __inline unsigned int
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mips_pg_cwpage_bit()
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{
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if (CPUISMIPS3)
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return (MIPS3_PG_CWPAGE);
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return (MIPS1_PG_CWPAGE);
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}
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static __inline unsigned int
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mips_pg_global_bit()
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{
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if (CPUISMIPS3)
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return (MIPS3_PG_G);
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return (MIPS1_PG_G);
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}
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static __inline unsigned int
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mips_pg_wired_bit()
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{
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if (CPUISMIPS3)
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return (MIPS3_PG_WIRED);
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return (MIPS1_PG_WIRED);
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}
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static __inline unsigned int
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PTE_TO_PADDR(pte)
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unsigned int pte;
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{
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if (CPUISMIPS3)
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return (MIPS3_PTE_TO_PADDR(pte));
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return (MIPS1_PTE_TO_PADDR(pte));
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}
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static __inline int
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PAGE_IS_RDONLY(pte, va)
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unsigned int pte;
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vm_offset_t va;
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{
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if (CPUISMIPS3)
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return (MIPS3_PAGE_IS_RDONLY(pte, va));
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return (MIPS1_PAGE_IS_RDONLY(pte, va));
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}
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static __inline vm_offset_t
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pfn_to_vad(x)
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unsigned int x;
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{
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if (CPUISMIPS3)
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return (mips3_pfn_to_vad(x));
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return (mips1_pfn_to_vad(x));
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}
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static __inline int
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vad_to_pfn(x)
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vm_offset_t x;
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{
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if (CPUISMIPS3)
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return (mips3_vad_to_pfn(x));
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return (mips1_vad_to_pfn(x));
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}
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#endif
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#endif /* ! _LOCORE */
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#if defined(_KERNEL) && !defined(_LOCORE)
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/*
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* Kernel virtual address to page table entry and visa versa.
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*/
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#define kvtopte(va) \
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(Sysmap + (((vm_offset_t)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT))
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#define ptetokv(pte) \
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((((pt_entry_t *)(pte) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS)
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extern pt_entry_t *Sysmap; /* kernel pte table */
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extern u_int Sysmapsize; /* number of pte's in Sysmap */
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#endif /* defined(_KERNEL) && !defined(_LOCORE) */
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/*
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* User virtual to pte page entry. Same on mips1 and mips3.
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*/
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#define uvtopte(adr) (((adr) >> PGSHIFT) & (NPTEPG - 1))
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#endif /* __MIPS_PTE_H__ */
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