f8ce8a3693
- don't erase FPSR exception bits _after_ doing most of the operations in fpu_implode(), erase them before doing arith and store operations. This fixes losing the DZ bit. - create FPSR_OVFL and FPSR_UNFL bits in fpu_implode(). This showed up when the first error was fixed. XXX some more work needs to be done. E.g., creating OPERR together with OVFL looks bogus, but I'm too tired know to re-check docs; and at least we pass our own regression tests know.
491 lines
14 KiB
C
491 lines
14 KiB
C
/* $NetBSD: fpu_implode.c,v 1.3 1997/07/19 22:28:50 is Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)fpu_implode.c 8.1 (Berkeley) 6/11/93
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*/
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/*
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* FPU subroutines: `implode' internal format numbers into the machine's
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* `packed binary' format.
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*/
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#include <sys/types.h>
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#include <sys/systm.h>
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#include "ieee.h"
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#include <machine/reg.h>
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#include "fpu_emulate.h"
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#include "fpu_arith.h"
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/* Conversion from internal format -- note asymmetry. */
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static u_int fpu_ftoi __P((struct fpemu *fe, struct fpn *fp));
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static u_int fpu_ftos __P((struct fpemu *fe, struct fpn *fp));
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static u_int fpu_ftod __P((struct fpemu *fe, struct fpn *fp, u_int *));
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static u_int fpu_ftox __P((struct fpemu *fe, struct fpn *fp, u_int *));
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/*
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* Round a number (algorithm from Motorola MC68882 manual, modified for
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* our internal format). Set inexact exception if rounding is required.
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* Return true iff we rounded up.
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*
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* After rounding, we discard the guard and round bits by shifting right
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* 2 bits (a la fpu_shr(), but we do not bother with fp->fp_sticky).
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* This saves effort later.
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*
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* Note that we may leave the value 2.0 in fp->fp_mant; it is the caller's
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* responsibility to fix this if necessary.
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*/
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int
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round(register struct fpemu *fe, register struct fpn *fp)
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{
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register u_int m0, m1, m2, m3;
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register int gr, s;
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m0 = fp->fp_mant[0];
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m1 = fp->fp_mant[1];
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m2 = fp->fp_mant[2];
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m3 = fp->fp_mant[3];
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gr = m3 & 3;
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s = fp->fp_sticky;
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/* mant >>= FP_NG */
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m3 = (m3 >> FP_NG) | (m2 << (32 - FP_NG));
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m2 = (m2 >> FP_NG) | (m1 << (32 - FP_NG));
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m1 = (m1 >> FP_NG) | (m0 << (32 - FP_NG));
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m0 >>= FP_NG;
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if ((gr | s) == 0) /* result is exact: no rounding needed */
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goto rounddown;
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fe->fe_fpsr |= FPSR_INEX2; /* inexact */
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/* Go to rounddown to round down; break to round up. */
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switch (fe->fe_fpcr & FPCR_ROUND) {
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case FPCR_NEAR:
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default:
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/*
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* Round only if guard is set (gr & 2). If guard is set,
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* but round & sticky both clear, then we want to round
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* but have a tie, so round to even, i.e., add 1 iff odd.
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*/
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if ((gr & 2) == 0)
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goto rounddown;
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if ((gr & 1) || fp->fp_sticky || (m3 & 1))
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break;
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goto rounddown;
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case FPCR_ZERO:
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/* Round towards zero, i.e., down. */
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goto rounddown;
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case FPCR_MINF:
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/* Round towards -Inf: up if negative, down if positive. */
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if (fp->fp_sign)
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break;
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goto rounddown;
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case FPCR_PINF:
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/* Round towards +Inf: up if positive, down otherwise. */
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if (!fp->fp_sign)
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break;
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goto rounddown;
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}
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/* Bump low bit of mantissa, with carry. */
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#ifdef sparc /* ``cheating'' (left out FPU_DECL_CARRY; know this is faster) */
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FPU_ADDS(m3, m3, 1);
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FPU_ADDCS(m2, m2, 0);
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FPU_ADDCS(m1, m1, 0);
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FPU_ADDC(m0, m0, 0);
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#else
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if (++m3 == 0 && ++m2 == 0 && ++m1 == 0)
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m0++;
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#endif
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fp->fp_mant[0] = m0;
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fp->fp_mant[1] = m1;
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fp->fp_mant[2] = m2;
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fp->fp_mant[3] = m3;
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return (1);
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rounddown:
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fp->fp_mant[0] = m0;
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fp->fp_mant[1] = m1;
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fp->fp_mant[2] = m2;
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fp->fp_mant[3] = m3;
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return (0);
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}
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/*
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* For overflow: return true if overflow is to go to +/-Inf, according
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* to the sign of the overflowing result. If false, overflow is to go
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* to the largest magnitude value instead.
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*/
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static int
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toinf(struct fpemu *fe, int sign)
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{
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int inf;
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/* look at rounding direction */
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switch (fe->fe_fpcr & FPCR_ROUND) {
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default:
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case FPCR_NEAR: /* the nearest value is always Inf */
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inf = 1;
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break;
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case FPCR_ZERO: /* toward 0 => never towards Inf */
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inf = 0;
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break;
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case FPCR_PINF: /* toward +Inf iff positive */
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inf = (sign == 0);
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break;
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case FPCR_MINF: /* toward -Inf iff negative */
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inf = sign;
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break;
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}
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return (inf);
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}
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/*
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* fpn -> int (int value returned as return value).
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*
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* N.B.: this conversion always rounds towards zero (this is a peculiarity
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* of the SPARC instruction set).
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*/
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static u_int
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fpu_ftoi(fe, fp)
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struct fpemu *fe;
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register struct fpn *fp;
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{
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register u_int i;
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register int sign, exp;
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sign = fp->fp_sign;
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switch (fp->fp_class) {
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case FPC_ZERO:
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return (0);
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case FPC_NUM:
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/*
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* If exp >= 2^32, overflow. Otherwise shift value right
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* into last mantissa word (this will not exceed 0xffffffff),
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* shifting any guard and round bits out into the sticky
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* bit. Then ``round'' towards zero, i.e., just set an
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* inexact exception if sticky is set (see round()).
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* If the result is > 0x80000000, or is positive and equals
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* 0x80000000, overflow; otherwise the last fraction word
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* is the result.
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*/
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if ((exp = fp->fp_exp) >= 32)
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break;
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/* NB: the following includes exp < 0 cases */
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if (fpu_shr(fp, FP_NMANT - 1 - FP_NG - exp) != 0)
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/* m68881/2 do not underflow when
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converting to integer */;
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round(fe, fp);
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i = fp->fp_mant[3];
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if (i >= ((u_int)0x80000000 + sign))
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break;
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return (sign ? -i : i);
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default: /* Inf, qNaN, sNaN */
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break;
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}
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/* overflow: replace any inexact exception with invalid */
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fe->fe_fpsr = (fe->fe_fpsr & ~FPSR_INEX2) | FPSR_OPERR;
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return (0x7fffffff + sign);
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}
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/*
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* fpn -> single (32 bit single returned as return value).
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* We assume <= 29 bits in a single-precision fraction (1.f part).
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*/
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static u_int
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fpu_ftos(fe, fp)
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struct fpemu *fe;
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register struct fpn *fp;
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{
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register u_int sign = fp->fp_sign << 31;
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register int exp;
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#define SNG_EXP(e) ((e) << SNG_FRACBITS) /* makes e an exponent */
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#define SNG_MASK (SNG_EXP(1) - 1) /* mask for fraction */
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/* Take care of non-numbers first. */
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if (ISNAN(fp)) {
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/*
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* Preserve upper bits of NaN, per SPARC V8 appendix N.
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* Note that fp->fp_mant[0] has the quiet bit set,
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* even if it is classified as a signalling NaN.
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*/
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(void) fpu_shr(fp, FP_NMANT - 1 - SNG_FRACBITS);
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exp = SNG_EXP_INFNAN;
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goto done;
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}
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if (ISINF(fp))
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return (sign | SNG_EXP(SNG_EXP_INFNAN));
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if (ISZERO(fp))
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return (sign);
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/*
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* Normals (including subnormals). Drop all the fraction bits
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* (including the explicit ``implied'' 1 bit) down into the
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* single-precision range. If the number is subnormal, move
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* the ``implied'' 1 into the explicit range as well, and shift
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* right to introduce leading zeroes. Rounding then acts
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* differently for normals and subnormals: the largest subnormal
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* may round to the smallest normal (1.0 x 2^minexp), or may
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* remain subnormal. In the latter case, signal an underflow
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* if the result was inexact or if underflow traps are enabled.
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*
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* Rounding a normal, on the other hand, always produces another
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* normal (although either way the result might be too big for
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* single precision, and cause an overflow). If rounding a
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* normal produces 2.0 in the fraction, we need not adjust that
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* fraction at all, since both 1.0 and 2.0 are zero under the
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* fraction mask.
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*
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* Note that the guard and round bits vanish from the number after
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* rounding.
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*/
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if ((exp = fp->fp_exp + SNG_EXP_BIAS) <= 0) { /* subnormal */
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fe->fe_fpsr |= FPSR_UNFL;
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/* -NG for g,r; -SNG_FRACBITS-exp for fraction */
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(void) fpu_shr(fp, FP_NMANT - FP_NG - SNG_FRACBITS - exp);
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if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(1))
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return (sign | SNG_EXP(1) | 0);
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if (fe->fe_fpsr & FPSR_INEX2)
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fe->fe_fpsr |= FPSR_UNFL
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/* mc68881/2 don't underflow when converting */;
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return (sign | SNG_EXP(0) | fp->fp_mant[3]);
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}
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/* -FP_NG for g,r; -1 for implied 1; -SNG_FRACBITS for fraction */
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(void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - SNG_FRACBITS);
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#ifdef DIAGNOSTIC
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if ((fp->fp_mant[3] & SNG_EXP(1 << FP_NG)) == 0)
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panic("fpu_ftos");
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#endif
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if (round(fe, fp) && fp->fp_mant[3] == SNG_EXP(2))
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exp++;
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if (exp >= SNG_EXP_INFNAN) {
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/* overflow to inf or to max single */
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fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2 | FPSR_OVFL;
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if (toinf(fe, sign))
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return (sign | SNG_EXP(SNG_EXP_INFNAN));
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return (sign | SNG_EXP(SNG_EXP_INFNAN - 1) | SNG_MASK);
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}
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done:
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/* phew, made it */
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return (sign | SNG_EXP(exp) | (fp->fp_mant[3] & SNG_MASK));
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}
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/*
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* fpn -> double (32 bit high-order result returned; 32-bit low order result
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* left in res[1]). Assumes <= 61 bits in double precision fraction.
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*
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* This code mimics fpu_ftos; see it for comments.
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*/
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static u_int
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fpu_ftod(fe, fp, res)
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struct fpemu *fe;
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register struct fpn *fp;
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u_int *res;
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{
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register u_int sign = fp->fp_sign << 31;
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register int exp;
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#define DBL_EXP(e) ((e) << (DBL_FRACBITS & 31))
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#define DBL_MASK (DBL_EXP(1) - 1)
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if (ISNAN(fp)) {
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(void) fpu_shr(fp, FP_NMANT - 1 - DBL_FRACBITS);
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exp = DBL_EXP_INFNAN;
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goto done;
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}
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if (ISINF(fp)) {
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sign |= DBL_EXP(DBL_EXP_INFNAN);
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res[1] = 0;
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return (sign);
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}
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if (ISZERO(fp)) {
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res[1] = 0;
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return (sign);
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}
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if ((exp = fp->fp_exp + DBL_EXP_BIAS) <= 0) {
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fe->fe_fpsr |= FPSR_UNFL;
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(void) fpu_shr(fp, FP_NMANT - FP_NG - DBL_FRACBITS - exp);
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if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(1)) {
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res[1] = 0;
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return (sign | DBL_EXP(1) | 0);
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}
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if (fe->fe_fpsr & FPSR_INEX2)
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fe->fe_fpsr |= FPSR_UNFL
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/* mc68881/2 don't underflow when converting */;
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exp = 0;
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goto done;
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}
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(void) fpu_shr(fp, FP_NMANT - FP_NG - 1 - DBL_FRACBITS);
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if (round(fe, fp) && fp->fp_mant[2] == DBL_EXP(2))
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exp++;
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if (exp >= DBL_EXP_INFNAN) {
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fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2 | FPSR_OVFL;
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if (toinf(fe, sign)) {
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res[1] = 0;
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return (sign | DBL_EXP(DBL_EXP_INFNAN) | 0);
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}
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res[1] = ~0;
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return (sign | DBL_EXP(DBL_EXP_INFNAN) | DBL_MASK);
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}
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done:
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res[1] = fp->fp_mant[3];
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return (sign | DBL_EXP(exp) | (fp->fp_mant[2] & DBL_MASK));
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}
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/*
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* fpn -> 68k extended (32 bit high-order result returned; two 32-bit low
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* order result left in res[1] & res[2]). Assumes == 64 bits in extended
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* precision fraction.
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*
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* This code mimics fpu_ftos; see it for comments.
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*/
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static u_int
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fpu_ftox(fe, fp, res)
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struct fpemu *fe;
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register struct fpn *fp;
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u_int *res;
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{
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register u_int sign = fp->fp_sign << 31;
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register int exp;
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#define EXT_EXP(e) ((e) << 16)
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#define EXT_MASK (EXT_EXP(1) - 1)
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if (ISNAN(fp)) {
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(void) fpu_shr(fp, FP_NMANT - 1 - EXT_FRACBITS);
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exp = EXT_EXP_INFNAN;
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goto done;
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}
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if (ISINF(fp)) {
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sign |= EXT_EXP(EXT_EXP_INFNAN);
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res[1] = res[2] = 0;
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return (sign);
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}
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if (ISZERO(fp)) {
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res[1] = res[2] = 0;
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return (sign);
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}
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if ((exp = fp->fp_exp + EXT_EXP_BIAS) <= 0) {
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fe->fe_fpsr |= FPSR_UNFL;
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/* I'm not sure about this <=... exp==0 doesn't mean
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it's a denormal in extended format */
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(void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS - exp);
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if (round(fe, fp) && fp->fp_mant[2] == EXT_EXP(1)) {
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res[1] = res[2] = 0;
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return (sign | EXT_EXP(1) | 0);
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}
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if (fe->fe_fpsr & FPSR_INEX2)
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fe->fe_fpsr |= FPSR_UNFL
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/* mc68881/2 don't underflow */;
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exp = 0;
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goto done;
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}
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(void) fpu_shr(fp, FP_NMANT - FP_NG - EXT_FRACBITS);
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if (round(fe, fp) && fp->fp_mant[2] == EXT_EXP(2))
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exp++;
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if (exp >= EXT_EXP_INFNAN) {
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fe->fe_fpsr |= FPSR_OPERR | FPSR_INEX2 | FPSR_OVFL;
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if (toinf(fe, sign)) {
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res[1] = res[2] = 0;
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return (sign | EXT_EXP(EXT_EXP_INFNAN) | 0);
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}
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res[1] = res[2] = ~0;
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return (sign | EXT_EXP(EXT_EXP_INFNAN) | EXT_MASK);
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}
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done:
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res[1] = fp->fp_mant[2];
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res[2] = fp->fp_mant[3];
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return (sign | EXT_EXP(exp));
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}
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/*
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* Implode an fpn, writing the result into the given space.
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*/
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void
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fpu_implode(fe, fp, type, space)
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struct fpemu *fe;
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register struct fpn *fp;
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int type;
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register u_int *space;
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{
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/* XXX Dont delete exceptions set here: fe->fe_fpsr &= ~FPSR_EXCP; */
|
|
|
|
switch (type) {
|
|
case FTYPE_LNG:
|
|
space[0] = fpu_ftoi(fe, fp);
|
|
break;
|
|
|
|
case FTYPE_SNG:
|
|
space[0] = fpu_ftos(fe, fp);
|
|
break;
|
|
|
|
case FTYPE_DBL:
|
|
space[0] = fpu_ftod(fe, fp, space);
|
|
break;
|
|
|
|
case FTYPE_EXT:
|
|
/* funky rounding precision options ?? */
|
|
space[0] = fpu_ftox(fe, fp, space);
|
|
break;
|
|
|
|
default:
|
|
panic("fpu_implode");
|
|
}
|
|
}
|