1271 lines
31 KiB
C
1271 lines
31 KiB
C
/* $NetBSD: seeq8005.c,v 1.7 2000/12/14 06:27:26 thorpej Exp $ */
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/*
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* Copyright (c) 2000 Ben Harris
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* Copyright (c) 1995 Mark Brinicombe
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* seeq8005.c - SEEQ 8005 device driver
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*/
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/*
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* This driver currently supports the following chip:
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* SEEQ 8005 Advanced Ethernet Data Link Controller
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*/
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/*
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* This driver is based on the arm32 ea(4) driver, hence the names of many
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* of the functions.
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*/
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/*
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* Bugs/possible improvements:
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* - Does not currently support DMA
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* - Does not currently support multicasts
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* - Does not transmit multiple packets in one go
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* - Does not support big-endian hosts
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* - Does not support 8-bit busses
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*/
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#include "opt_inet.h"
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#include "opt_ns.h"
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#include <sys/types.h>
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#include <sys/param.h>
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__RCSID("$NetBSD: seeq8005.c,v 1.7 2000/12/14 06:27:26 thorpej Exp $");
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_types.h>
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#include <net/if_ether.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/in_systm.h>
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#include <netinet/in_var.h>
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#include <netinet/ip.h>
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#include <netinet/if_inarp.h>
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#endif
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#include "bpfilter.h"
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#include <net/bpfdesc.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/ic/seeq8005reg.h>
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#include <dev/ic/seeq8005var.h>
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#ifndef EA_TIMEOUT
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#define EA_TIMEOUT 60
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#endif
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#define EA_TX_BUFFER_SIZE 0x4000
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#define EA_RX_BUFFER_SIZE 0xC000
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/*#define EA_TX_DEBUG*/
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/*#define EA_RX_DEBUG*/
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/*#define EA_DEBUG*/
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/*#define EA_PACKET_DEBUG*/
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/* for debugging convenience */
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#ifdef EA_DEBUG
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#define dprintf(x) printf x
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#else
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#define dprintf(x)
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#endif
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/*
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* prototypes
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*/
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static int ea_init(struct ifnet *);
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static int ea_ioctl(struct ifnet *, u_long, caddr_t);
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static void ea_start(struct ifnet *);
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static void ea_watchdog(struct ifnet *);
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static void ea_chipreset(struct seeq8005_softc *);
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static void ea_ramtest(struct seeq8005_softc *);
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static int ea_stoptx(struct seeq8005_softc *);
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static int ea_stoprx(struct seeq8005_softc *);
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static void ea_stop(struct ifnet *, int);
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static void ea_await_fifo_empty(struct seeq8005_softc *);
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static void ea_await_fifo_full(struct seeq8005_softc *);
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static void ea_writebuf(struct seeq8005_softc *, u_char *, u_int, size_t);
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static void ea_readbuf(struct seeq8005_softc *, u_char *, u_int, size_t);
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static void ea_select_buffer(struct seeq8005_softc *, int);
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static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *);
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static void earead(struct seeq8005_softc *, int, int);
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static struct mbuf *eaget(struct seeq8005_softc *, int, int, struct ifnet *);
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static void eagetpackets(struct seeq8005_softc *);
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static void eatxpacket(struct seeq8005_softc *);
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static void ea_mc_reset(struct seeq8005_softc *);
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#ifdef EA_PACKET_DEBUG
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void ea_dump_buffer(struct seeq8005_softc *, int);
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#endif
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#ifdef EA_PACKET_DEBUG
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/*
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* Dump the interface buffer
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*/
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void
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ea_dump_buffer(struct seeq8005_softc *sc, u_int offset)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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u_int addr;
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int loop, ctrl, ptr;
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size_t size;
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addr = offset;
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do {
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bus_space_write_2(iot, ioh, EA_8005_COMMAND,
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sc->sc_command | EA_CMD_FIFO_READ);
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bus_space_write_2(iot, ioh, EA_8005_CONFIG1,
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sc->sc_config1 | EA_BUFCODE_LOCAL_MEM);
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bus_space_write_2(iot, ioh, EA_8005_DMA_ADDR, addr);
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ptr = bus_space_read_2(iot, ioh, EA_8005_BUFWIN);
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ctrl = bus_space_read_2(iot, ioh, EA_8005_BUFWIN);
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ptr = ((ptr & 0xff) << 8) | ((ptr >> 8) & 0xff);
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if (ptr == 0) break;
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size = ptr - addr;
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printf("addr=%04x size=%04x ", addr, size);
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printf("cmd=%02x st=%02x\n", ctrl & 0xff, ctrl >> 8);
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for (loop = 0; loop < size - 4; loop += 2)
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printf("%04x ",
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bus_space_read_2(iot, ioh, EA_8005_BUFWIN));
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printf("\n");
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addr = ptr;
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} while (size != 0);
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}
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#endif
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/*
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* Attach chip.
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*/
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void
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seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr)
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{
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struct ifnet *ifp = &sc->sc_ethercom.ec_if;
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u_int id;
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printf(" address %s", ether_sprintf(myaddr));
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/* Stop the board. */
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ea_chipreset(sc);
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/* Get the product ID */
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ea_select_buffer(sc, EA_BUFCODE_PRODUCTID);
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id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EA_8005_BUFWIN);
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if ((id & 0xf0) == 0xa0) {
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sc->sc_flags |= SEEQ8005_80C04;
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printf(", SEEQ 80C04 rev %02x", id);
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} else
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printf(", SEEQ 8005");
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/* Initialise ifnet structure. */
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bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
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ifp->if_softc = sc;
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ifp->if_start = ea_start;
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ifp->if_ioctl = ea_ioctl;
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ifp->if_init = ea_init;
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ifp->if_stop = ea_stop;
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ifp->if_watchdog = ea_watchdog;
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ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS;
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IFQ_SET_READY(&ifp->if_snd);
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/* Now we can attach the interface. */
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if_attach(ifp);
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ether_ifattach(ifp, myaddr);
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printf("\n");
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/* Test the RAM */
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ea_ramtest(sc);
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}
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/*
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* Test the RAM on the ethernet card.
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*/
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void
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ea_ramtest(struct seeq8005_softc *sc)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int loop;
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u_int sum = 0;
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/* dprintf(("ea_ramtest()\n"));*/
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/*
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* Test the buffer memory on the board.
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* Write simple pattens to it and read them back.
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*/
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/* Set up the whole buffer RAM for writing */
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ea_select_buffer(sc, EA_BUFCODE_TX_EAP);
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bus_space_write_2(iot, ioh, EA_8005_BUFWIN, (EA_BUFFER_SIZE >> 8) - 1);
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bus_space_write_2(iot, ioh, EA_8005_TX_PTR, 0x0000);
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bus_space_write_2(iot, ioh, EA_8005_RX_PTR, EA_BUFFER_SIZE - 2);
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#define EA_RAMTEST_LOOP(value) \
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do { \
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/* Set the write start address and write a pattern */ \
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ea_writebuf(sc, NULL, 0x0000, 0); \
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for (loop = 0; loop < EA_BUFFER_SIZE; loop += 2) \
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bus_space_write_2(iot, ioh, EA_8005_BUFWIN, (value)); \
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\
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/* Set the read start address and verify the pattern */ \
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ea_readbuf(sc, NULL, 0x0000, 0); \
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for (loop = 0; loop < EA_BUFFER_SIZE; loop += 2) \
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if (bus_space_read_2(iot, ioh, EA_8005_BUFWIN) != (value)) \
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++sum; \
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if (sum != 0) \
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dprintf(("sum=%d\n", sum)); \
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} while (/*CONSTCOND*/0)
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EA_RAMTEST_LOOP(loop);
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EA_RAMTEST_LOOP(loop ^ (EA_BUFFER_SIZE - 1));
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EA_RAMTEST_LOOP(0xaa55);
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EA_RAMTEST_LOOP(0x55aa);
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/* Report */
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if (sum > 0)
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printf("%s: buffer RAM failed self test, %d faults\n",
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sc->sc_dev.dv_xname, sum);
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}
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/*
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* Stop the tx interface.
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*
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* Returns 0 if the tx was already stopped or 1 if it was active
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*/
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static int
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ea_stoptx(struct seeq8005_softc *sc)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int timeout;
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int status;
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dprintf(("ea_stoptx()\n"));
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status = bus_space_read_2(iot, ioh, EA_8005_STATUS);
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if (!(status & EA_STATUS_TX_ON))
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return 0;
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/* Stop any tx and wait for confirmation */
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bus_space_write_2(iot, ioh, EA_8005_COMMAND,
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sc->sc_command | EA_CMD_TX_OFF);
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timeout = 20000;
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do {
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status = bus_space_read_2(iot, ioh, EA_8005_STATUS);
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} while ((status & EA_STATUS_TX_ON) && --timeout > 0);
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if (timeout == 0)
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dprintf(("ea_stoptx: timeout waiting for tx termination\n"));
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/* Clear any pending tx interrupt */
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bus_space_write_2(iot, ioh, EA_8005_COMMAND,
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sc->sc_command | EA_CMD_TX_INTACK);
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return 1;
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}
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/*
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* Stop the rx interface.
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*
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* Returns 0 if the tx was already stopped or 1 if it was active
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*/
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static int
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ea_stoprx(struct seeq8005_softc *sc)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int timeout;
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int status;
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dprintf(("ea_stoprx()\n"));
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status = bus_space_read_2(iot, ioh, EA_8005_STATUS);
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if (!(status & EA_STATUS_RX_ON))
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return 0;
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/* Stop any rx and wait for confirmation */
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bus_space_write_2(iot, ioh, EA_8005_COMMAND,
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sc->sc_command | EA_CMD_RX_OFF);
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timeout = 20000;
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do {
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status = bus_space_read_2(iot, ioh, EA_8005_STATUS);
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} while ((status & EA_STATUS_RX_ON) && --timeout > 0);
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if (timeout == 0)
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dprintf(("ea_stoprx: timeout waiting for rx termination\n"));
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/* Clear any pending rx interrupt */
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bus_space_write_2(iot, ioh, EA_8005_COMMAND,
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sc->sc_command | EA_CMD_RX_INTACK);
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return 1;
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}
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/*
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* Stop interface.
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* Stop all IO and shut the interface down
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*/
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static void
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ea_stop(struct ifnet *ifp, int disable)
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{
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struct seeq8005_softc *sc = ifp->if_softc;
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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dprintf(("ea_stop()\n"));
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/* Stop all IO */
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ea_stoptx(sc);
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ea_stoprx(sc);
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/* Disable rx and tx interrupts */
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sc->sc_command &= (EA_CMD_RX_INTEN | EA_CMD_TX_INTEN);
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/* Clear any pending interrupts */
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bus_space_write_2(iot, ioh, EA_8005_COMMAND,
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sc->sc_command | EA_CMD_RX_INTACK |
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EA_CMD_TX_INTACK | EA_CMD_DMA_INTACK |
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EA_CMD_BW_INTACK);
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dprintf(("st=%08x", bus_space_read_2(iot, ioh, EA_8005_STATUS)));
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/* Cancel any watchdog timer */
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sc->sc_ethercom.ec_if.if_timer = 0;
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}
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/*
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* Reset the chip
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* Following this the software registers are reset
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*/
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static void
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ea_chipreset(struct seeq8005_softc *sc)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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dprintf(("ea_chipreset()\n"));
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/* Reset the controller. Min of 4us delay here */
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bus_space_write_2(iot, ioh, EA_8005_CONFIG2, EA_CFG2_RESET);
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delay(4);
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sc->sc_command = 0;
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sc->sc_config1 = 0;
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sc->sc_config2 = 0;
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}
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/*
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* If the DMA FIFO's in write mode, wait for it to empty. Needed when
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* switching the FIFO from write to read. We also use it when changing
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* the address for writes.
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*/
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static void
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ea_await_fifo_empty(struct seeq8005_softc *sc)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int timeout;
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timeout = 20000;
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if ((bus_space_read_2(iot, ioh, EA_8005_STATUS) &
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EA_STATUS_FIFO_DIR) != 0)
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return; /* FIFO is reading anyway. */
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while ((bus_space_read_2(iot, ioh, EA_8005_STATUS) &
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EA_STATUS_FIFO_EMPTY) == 0 &&
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--timeout > 0)
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continue;
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}
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/*
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* Wait for the DMA FIFO to fill before reading from it.
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*/
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static void
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ea_await_fifo_full(struct seeq8005_softc *sc)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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int timeout;
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timeout = 20000;
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while ((bus_space_read_2(iot, ioh, EA_8005_STATUS) &
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EA_STATUS_FIFO_FULL) == 0 &&
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--timeout > 0)
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continue;
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}
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/*
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* write to the buffer memory on the interface
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*
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* The buffer address is set to ADDR.
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* If len != 0 then data is copied from the address starting at buf
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* to the interface buffer.
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* BUF must be usable as a u_int16_t *.
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* If LEN is odd, it must be safe to overwrite one extra byte.
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*/
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static void
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ea_writebuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len)
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{
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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dprintf(("writebuf: st=%04x\n",
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bus_space_read_2(iot, ioh, EA_8005_STATUS)));
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#ifdef DIAGNOSTIC
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if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t)))
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panic("%s: unaligned writebuf", sc->sc_dev.dv_xname);
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#endif
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if (__predict_false(addr >= EA_BUFFER_SIZE))
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panic("%s: writebuf out of range", sc->sc_dev.dv_xname);
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/* Assume that copying too much is safe. */
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if (len % 2 != 0)
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len++;
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ea_await_fifo_empty(sc);
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|
|
ea_select_buffer(sc, EA_BUFCODE_LOCAL_MEM);
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND,
|
|
sc->sc_command | EA_CMD_FIFO_WRITE);
|
|
bus_space_write_2(iot, ioh, EA_8005_DMA_ADDR, addr);
|
|
|
|
if (len > 0)
|
|
bus_space_write_multi_2(iot, ioh, EA_8005_BUFWIN,
|
|
(u_int16_t *)buf, len / 2);
|
|
/* Leave FIFO to empty in the background */
|
|
}
|
|
|
|
|
|
/*
|
|
* read from the buffer memory on the interface
|
|
*
|
|
* The buffer address is set to ADDR.
|
|
* If len != 0 then data is copied from the interface buffer to the
|
|
* address starting at buf.
|
|
* BUF must be usable as a u_int16_t *.
|
|
* If LEN is odd, it must be safe to overwrite one extra byte.
|
|
*/
|
|
|
|
static void
|
|
ea_readbuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len)
|
|
{
|
|
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
|
|
|
dprintf(("readbuf: st=%04x addr=%04x len=%d\n",
|
|
bus_space_read_2(iot, ioh, EA_8005_STATUS), addr, len));
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (!ALIGNED_POINTER(buf, u_int16_t))
|
|
panic("%s: unaligned readbuf", sc->sc_dev.dv_xname);
|
|
#endif
|
|
if (addr >= EA_BUFFER_SIZE)
|
|
panic("%s: writebuf out of range", sc->sc_dev.dv_xname);
|
|
|
|
/* Assume that copying too much is safe. */
|
|
if (len % 2 != 0)
|
|
len++;
|
|
|
|
ea_await_fifo_empty(sc);
|
|
|
|
ea_select_buffer(sc, EA_BUFCODE_LOCAL_MEM);
|
|
bus_space_write_2(iot, ioh, EA_8005_DMA_ADDR, addr);
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND,
|
|
sc->sc_command | EA_CMD_FIFO_READ);
|
|
|
|
ea_await_fifo_full(sc);
|
|
|
|
if (len > 0)
|
|
bus_space_read_multi_2(iot, ioh, EA_8005_BUFWIN,
|
|
(u_int16_t *)buf, len / 2);
|
|
}
|
|
|
|
static void
|
|
ea_select_buffer(struct seeq8005_softc *sc, int bufcode)
|
|
{
|
|
|
|
bus_space_write_2(sc->sc_iot, sc->sc_ioh, EA_8005_CONFIG1,
|
|
sc->sc_config1 | bufcode);
|
|
}
|
|
|
|
/* Must be called at splnet */
|
|
static void
|
|
ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea)
|
|
{
|
|
int i;
|
|
|
|
ea_select_buffer(sc, EA_BUFCODE_STATION_ADDR0 + which);
|
|
for (i = 0; i < ETHER_ADDR_LEN; ++i)
|
|
bus_space_write_2(sc->sc_iot, sc->sc_ioh, EA_8005_BUFWIN,
|
|
ea[i]);
|
|
}
|
|
|
|
/*
|
|
* Initialize interface.
|
|
*
|
|
* This should leave the interface in a state for packet reception and
|
|
* transmission.
|
|
*/
|
|
|
|
static int
|
|
ea_init(struct ifnet *ifp)
|
|
{
|
|
struct seeq8005_softc *sc = ifp->if_softc;
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
|
int s;
|
|
|
|
dprintf(("ea_init()\n"));
|
|
|
|
s = splnet();
|
|
|
|
/* First, reset the board. */
|
|
|
|
ea_chipreset(sc);
|
|
|
|
/* Set up defaults for the registers */
|
|
|
|
sc->sc_command = 0x00;
|
|
sc->sc_config1 = 0x00; /* XXX DMA settings? */
|
|
#if BYTE_ORDER == BIG_ENDIAN
|
|
sc->sc_config2 = EA_CFG2_BYTESWAP
|
|
#else
|
|
sc->sc_config2 = 0;
|
|
#endif
|
|
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND, sc->sc_command);
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG1, sc->sc_config1);
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2);
|
|
|
|
/* Split board memory into Rx and Tx. */
|
|
ea_select_buffer(sc, EA_BUFCODE_TX_EAP);
|
|
bus_space_write_2(iot, ioh, EA_8005_BUFWIN,
|
|
(EA_TX_BUFFER_SIZE >> 8) - 1);
|
|
|
|
/* Write the station address - the receiver must be off */
|
|
ea_set_address(sc, 0, LLADDR(ifp->if_sadl));
|
|
|
|
/* Configure rx. */
|
|
dprintf(("Configuring rx...\n"));
|
|
if (ifp->if_flags & IFF_PROMISC)
|
|
sc->sc_config1 = EA_CFG1_PROMISCUOUS;
|
|
else
|
|
sc->sc_config1 = EA_CFG1_BROADCAST;
|
|
sc->sc_config1 |= EA_CFG1_STATION_ADDR0;
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG1, sc->sc_config1);
|
|
|
|
/* Setup the Rx pointers */
|
|
sc->sc_rx_ptr = EA_TX_BUFFER_SIZE;
|
|
|
|
bus_space_write_2(iot, ioh, EA_8005_RX_PTR, sc->sc_rx_ptr);
|
|
bus_space_write_2(iot, ioh, EA_8005_RX_END, sc->sc_rx_ptr >> 8);
|
|
|
|
|
|
/* Place a NULL header at the beginning of the receive area */
|
|
ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0);
|
|
|
|
bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000);
|
|
bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000);
|
|
|
|
|
|
/* Turn on Rx */
|
|
sc->sc_command |= EA_CMD_RX_INTEN;
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND,
|
|
sc->sc_command | EA_CMD_RX_ON);
|
|
|
|
|
|
/* Configure TX. */
|
|
dprintf(("Configuring tx...\n"));
|
|
|
|
bus_space_write_2(iot, ioh, EA_8005_TX_PTR, 0x0000);
|
|
|
|
sc->sc_config2 |= EA_CFG2_OUTPUT;
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2);
|
|
|
|
|
|
/* Place a NULL header at the beginning of the transmit area */
|
|
ea_writebuf(sc, NULL, 0x0000, 0);
|
|
|
|
bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000);
|
|
bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000);
|
|
|
|
sc->sc_command |= EA_CMD_TX_INTEN;
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND, sc->sc_command);
|
|
|
|
/* TX_ON gets set by ea_txpacket when there's something to transmit. */
|
|
|
|
|
|
/* Set flags appropriately. */
|
|
ifp->if_flags |= IFF_RUNNING;
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
dprintf(("init: st=%04x\n",
|
|
bus_space_read_2(iot, ioh, EA_8005_STATUS)));
|
|
|
|
|
|
/* And start output. */
|
|
ea_start(ifp);
|
|
|
|
splx(s);
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Start output on interface. Get datagrams from the queue and output them,
|
|
* giving the receiver a chance between datagrams. Call only from splnet or
|
|
* interrupt level!
|
|
*/
|
|
|
|
static void
|
|
ea_start(struct ifnet *ifp)
|
|
{
|
|
struct seeq8005_softc *sc = ifp->if_softc;
|
|
int s;
|
|
|
|
s = splnet();
|
|
#ifdef EA_TX_DEBUG
|
|
dprintf(("ea_start()...\n"));
|
|
#endif
|
|
|
|
/* Don't do anything if output is active. */
|
|
|
|
if (ifp->if_flags & IFF_OACTIVE)
|
|
return;
|
|
|
|
/* Mark interface as output active */
|
|
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
|
|
/* tx packets */
|
|
|
|
eatxpacket(sc);
|
|
splx(s);
|
|
}
|
|
|
|
|
|
/*
|
|
* Transfer a packet to the interface buffer and start transmission
|
|
*
|
|
* Called at splnet()
|
|
*/
|
|
|
|
void
|
|
eatxpacket(struct seeq8005_softc *sc)
|
|
{
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
|
struct mbuf *m, *m0;
|
|
struct ifnet *ifp;
|
|
int len, nextpacket;
|
|
u_int8_t hdr[4];
|
|
|
|
ifp = &sc->sc_ethercom.ec_if;
|
|
|
|
/* Dequeue the next packet. */
|
|
IFQ_DEQUEUE(&ifp->if_snd, m0);
|
|
|
|
/* If there's nothing to send, return. */
|
|
if (!m0) {
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
sc->sc_config2 |= EA_CFG2_OUTPUT;
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2);
|
|
#ifdef EA_TX_DEBUG
|
|
dprintf(("tx finished\n"));
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
#if NBPFILTER > 0
|
|
/* Give the packet to the bpf, if any. */
|
|
if (ifp->if_bpf)
|
|
bpf_mtap(ifp->if_bpf, m0);
|
|
#endif
|
|
|
|
#ifdef EA_TX_DEBUG
|
|
dprintf(("Tx new packet\n"));
|
|
#endif
|
|
|
|
sc->sc_config2 &= ~EA_CFG2_OUTPUT;
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2);
|
|
|
|
/*
|
|
* Copy the frame to the start of the transmit area on the card,
|
|
* leaving four bytes for the transmit header.
|
|
*/
|
|
len = 0;
|
|
for (m = m0; m; m = m->m_next) {
|
|
if (m->m_len == 0)
|
|
continue;
|
|
ea_writebuf(sc, mtod(m, caddr_t), 4 + len, m->m_len);
|
|
len += m->m_len;
|
|
}
|
|
m_freem(m0);
|
|
|
|
|
|
/* If packet size is odd round up to the next 16 bit boundry */
|
|
if (len % 2)
|
|
++len;
|
|
|
|
len = max(len, ETHER_MIN_LEN);
|
|
|
|
if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN))
|
|
log(LOG_WARNING, "%s: oversize packet = %d bytes\n",
|
|
sc->sc_dev.dv_xname, len);
|
|
|
|
#if 0 /*def EA_TX_DEBUG*/
|
|
dprintf(("ea: xfr pkt length=%d...\n", len));
|
|
|
|
dprintf(("%s-->", ether_sprintf(sc->sc_pktbuf+6)));
|
|
dprintf(("%s\n", ether_sprintf(sc->sc_pktbuf)));
|
|
#endif
|
|
|
|
/* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));*/
|
|
|
|
/* Follow it with a NULL packet header */
|
|
bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000);
|
|
bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000);
|
|
|
|
|
|
/* Write the packet header */
|
|
|
|
nextpacket = len + 4;
|
|
hdr[0] = (nextpacket >> 8) & 0xff;
|
|
hdr[1] = nextpacket & 0xff;
|
|
hdr[2] = EA_PKTHDR_TX | EA_PKTHDR_DATA_FOLLOWS |
|
|
EA_TXHDR_XMIT_SUCCESS_INT | EA_TXHDR_COLLISION_INT;
|
|
hdr[3] = 0; /* Status byte -- will be update by hardware. */
|
|
ea_writebuf(sc, hdr, 0x0000, 4);
|
|
|
|
bus_space_write_2(iot, ioh, EA_8005_TX_PTR, 0x0000);
|
|
|
|
/* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));*/
|
|
|
|
#ifdef EA_PACKET_DEBUG
|
|
ea_dump_buffer(sc, 0);
|
|
#endif
|
|
|
|
|
|
/* Now transmit the datagram. */
|
|
/* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));*/
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND,
|
|
sc->sc_command | EA_CMD_TX_ON);
|
|
#ifdef EA_TX_DEBUG
|
|
dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));
|
|
dprintf(("tx: queued\n"));
|
|
#endif
|
|
}
|
|
|
|
|
|
/*
|
|
* Ethernet controller interrupt.
|
|
*/
|
|
|
|
int
|
|
seeq8005intr(void *arg)
|
|
{
|
|
struct seeq8005_softc *sc = arg;
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
|
struct ifnet *ifp = &sc->sc_ethercom.ec_if;
|
|
int status, s, handled;
|
|
u_int8_t txhdr[4];
|
|
u_int txstatus;
|
|
|
|
handled = 0;
|
|
dprintf(("eaintr: "));
|
|
|
|
|
|
/* Get the controller status */
|
|
status = bus_space_read_2(iot, ioh, EA_8005_STATUS);
|
|
dprintf(("st=%04x ", status));
|
|
|
|
|
|
/* Tx interrupt ? */
|
|
if (status & EA_STATUS_TX_INT) {
|
|
dprintf(("txint "));
|
|
handled = 1;
|
|
|
|
/* Acknowledge the interrupt */
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND,
|
|
sc->sc_command | EA_CMD_TX_INTACK);
|
|
|
|
ea_readbuf(sc, txhdr, 0x0000, 4);
|
|
|
|
#ifdef EA_TX_DEBUG
|
|
dprintf(("txstatus=%02x %02x %02x %02x\n",
|
|
txhdr[0], txhdr[1], txhdr[2], txhdr[3]));
|
|
#endif
|
|
txstatus = txhdr[3];
|
|
|
|
/*
|
|
* Did it succeed ? Did we collide ?
|
|
*
|
|
* The exact proceedure here is not clear. We should get
|
|
* an interrupt on a sucessfull tx or on a collision.
|
|
* The done flag is set after successfull tx or 16 collisions
|
|
* We should thus get a interrupt for each of collision
|
|
* and the done bit should not be set. However it does appear
|
|
* to be set at the same time as the collision bit ...
|
|
*
|
|
* So we will count collisions and output errors and will
|
|
* assume that if the done bit is set the packet was
|
|
* transmitted. Stats may be wrong if 16 collisions occur on
|
|
* a packet as the done flag should be set but the packet
|
|
* may not have been transmitted. so the output count might
|
|
* not require incrementing if the 16 collisions flags is
|
|
* set. I don;t know abou this until it happens.
|
|
*/
|
|
|
|
if (txstatus & EA_TXHDR_COLLISION)
|
|
ifp->if_collisions++;
|
|
else if (txstatus & EA_TXHDR_ERROR_MASK)
|
|
ifp->if_oerrors++;
|
|
|
|
#if 0
|
|
if (txstatus & EA_TXHDR_ERROR_MASK)
|
|
log(LOG_WARNING, "tx packet error =%02x\n", txstatus);
|
|
#endif
|
|
|
|
if (txstatus & EA_PKTHDR_DONE) {
|
|
ifp->if_opackets++;
|
|
|
|
/* Tx next packet */
|
|
|
|
s = splnet();
|
|
eatxpacket(sc);
|
|
splx(s);
|
|
}
|
|
}
|
|
|
|
|
|
/* Rx interrupt ? */
|
|
if (status & EA_STATUS_RX_INT) {
|
|
dprintf(("rxint "));
|
|
handled = 1;
|
|
|
|
/* Acknowledge the interrupt */
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND,
|
|
sc->sc_command | EA_CMD_RX_INTACK);
|
|
|
|
/* Install a watchdog timer needed atm to fixed rx lockups */
|
|
ifp->if_timer = EA_TIMEOUT;
|
|
|
|
/* Processes the received packets */
|
|
eagetpackets(sc);
|
|
|
|
|
|
#if 0
|
|
/* Make sure the receiver is on */
|
|
if ((status & EA_STATUS_RX_ON) == 0) {
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND,
|
|
sc->sc_command | EA_CMD_RX_ON);
|
|
printf("rxintr: rx is off st=%04x\n",status);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#ifdef EA_DEBUG
|
|
status = bus_space_read_2(iot, ioh, EA_8005_STATUS);
|
|
dprintf(("st=%04x\n", status));
|
|
#endif
|
|
|
|
return handled;
|
|
}
|
|
|
|
|
|
void
|
|
eagetpackets(struct seeq8005_softc *sc)
|
|
{
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
|
u_int addr;
|
|
int len;
|
|
int ctrl;
|
|
int ptr;
|
|
int pack;
|
|
int status;
|
|
u_int8_t rxhdr[4];
|
|
struct ifnet *ifp;
|
|
|
|
ifp = &sc->sc_ethercom.ec_if;
|
|
|
|
|
|
/* We start from the last rx pointer position */
|
|
addr = sc->sc_rx_ptr;
|
|
sc->sc_config2 &= ~EA_CFG2_OUTPUT;
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2);
|
|
|
|
do {
|
|
/* Read rx header */
|
|
ea_readbuf(sc, rxhdr, addr, 4);
|
|
|
|
/* Split the packet header */
|
|
ptr = (rxhdr[0] << 8) | rxhdr[1];
|
|
ctrl = rxhdr[2];
|
|
status = rxhdr[3];
|
|
|
|
#ifdef EA_RX_DEBUG
|
|
dprintf(("addr=%04x ptr=%04x ctrl=%02x status=%02x\n",
|
|
addr, ptr, ctrl, status));
|
|
#endif
|
|
|
|
|
|
/* Zero packet ptr ? then must be null header so exit */
|
|
if (ptr == 0) break;
|
|
|
|
|
|
/* Get packet length */
|
|
len = (ptr - addr) - 4;
|
|
|
|
if (len < 0)
|
|
len += EA_RX_BUFFER_SIZE;
|
|
|
|
#ifdef EA_RX_DEBUG
|
|
dprintf(("len=%04x\n", len));
|
|
#endif
|
|
|
|
|
|
/* Has the packet rx completed ? if not then exit */
|
|
if ((status & EA_PKTHDR_DONE) == 0)
|
|
break;
|
|
|
|
/*
|
|
* Did we have any errors? then note error and go to
|
|
* next packet
|
|
*/
|
|
if (__predict_false(status & 0x0f)) {
|
|
++ifp->if_ierrors;
|
|
log(LOG_WARNING,
|
|
"%s: rx packet error (%02x) - dropping packet\n",
|
|
sc->sc_dev.dv_xname, status & 0x0f);
|
|
sc->sc_config2 |= EA_CFG2_OUTPUT;
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG2,
|
|
sc->sc_config2);
|
|
ea_init(ifp);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Is the packet too big ? - this will probably be trapped
|
|
* above as a receive error
|
|
*/
|
|
if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) {
|
|
++ifp->if_ierrors;
|
|
log(LOG_WARNING, "%s: rx packet size error len=%d\n",
|
|
sc->sc_dev.dv_xname, len);
|
|
sc->sc_config2 |= EA_CFG2_OUTPUT;
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG2,
|
|
sc->sc_config2);
|
|
ea_init(ifp);
|
|
return;
|
|
}
|
|
|
|
ifp->if_ipackets++;
|
|
/* Pass data up to upper levels. */
|
|
earead(sc, addr + 4, len);
|
|
|
|
addr = ptr;
|
|
++pack;
|
|
} while (len != 0);
|
|
|
|
sc->sc_config2 |= EA_CFG2_OUTPUT;
|
|
bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2);
|
|
|
|
#ifdef EA_RX_DEBUG
|
|
dprintf(("new rx ptr=%04x\n", addr));
|
|
#endif
|
|
|
|
|
|
/* Store new rx pointer */
|
|
sc->sc_rx_ptr = addr;
|
|
bus_space_write_2(iot, ioh, EA_8005_RX_END, sc->sc_rx_ptr >> 8);
|
|
|
|
/* Make sure the receiver is on */
|
|
bus_space_write_2(iot, ioh, EA_8005_COMMAND,
|
|
sc->sc_command | EA_CMD_RX_ON);
|
|
|
|
}
|
|
|
|
|
|
/*
|
|
* Pass a packet up to the higher levels.
|
|
*/
|
|
|
|
static void
|
|
earead(struct seeq8005_softc *sc, int addr, int len)
|
|
{
|
|
struct mbuf *m;
|
|
struct ifnet *ifp;
|
|
|
|
ifp = &sc->sc_ethercom.ec_if;
|
|
|
|
/* Pull packet off interface. */
|
|
m = eaget(sc, addr, len, ifp);
|
|
if (m == 0)
|
|
return;
|
|
|
|
#ifdef EA_RX_DEBUG
|
|
dprintf(("%s-->", ether_sprintf(eh->ether_shost)));
|
|
dprintf(("%s\n", ether_sprintf(eh->ether_dhost)));
|
|
#endif
|
|
|
|
#if NBPFILTER > 0
|
|
/*
|
|
* Check if there's a BPF listener on this interface.
|
|
* If so, hand off the raw packet to bpf.
|
|
*/
|
|
if (ifp->if_bpf)
|
|
bpf_mtap(ifp->if_bpf, m);
|
|
#endif
|
|
|
|
(*ifp->if_input)(ifp, m);
|
|
}
|
|
|
|
/*
|
|
* Pull read data off a interface. Len is length of data, with local net
|
|
* header stripped. We copy the data into mbufs. When full cluster sized
|
|
* units are present we copy into clusters.
|
|
*/
|
|
|
|
struct mbuf *
|
|
eaget(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp)
|
|
{
|
|
struct mbuf *top, **mp, *m;
|
|
int len;
|
|
u_int cp, epkt;
|
|
|
|
cp = addr;
|
|
epkt = cp + totlen;
|
|
|
|
MGETHDR(m, M_DONTWAIT, MT_DATA);
|
|
if (m == 0)
|
|
return 0;
|
|
m->m_pkthdr.rcvif = ifp;
|
|
m->m_pkthdr.len = totlen;
|
|
m->m_len = MHLEN;
|
|
top = 0;
|
|
mp = ⊤
|
|
|
|
while (totlen > 0) {
|
|
if (top) {
|
|
MGET(m, M_DONTWAIT, MT_DATA);
|
|
if (m == 0) {
|
|
m_freem(top);
|
|
return 0;
|
|
}
|
|
m->m_len = MLEN;
|
|
}
|
|
len = min(totlen, epkt - cp);
|
|
if (len >= MINCLSIZE) {
|
|
MCLGET(m, M_DONTWAIT);
|
|
if (m->m_flags & M_EXT)
|
|
m->m_len = len = min(len, MCLBYTES);
|
|
else
|
|
len = m->m_len;
|
|
} else {
|
|
/*
|
|
* Place initial small packet/header at end of mbuf.
|
|
*/
|
|
if (len < m->m_len) {
|
|
if (top == 0 && len + max_linkhdr <= m->m_len)
|
|
m->m_data += max_linkhdr;
|
|
m->m_len = len;
|
|
} else
|
|
len = m->m_len;
|
|
}
|
|
if (top == 0) {
|
|
/* Make sure the payload is aligned */
|
|
caddr_t newdata = (caddr_t)
|
|
ALIGN(m->m_data + sizeof(struct ether_header)) -
|
|
sizeof(struct ether_header);
|
|
len -= newdata - m->m_data;
|
|
m->m_len = len;
|
|
m->m_data = newdata;
|
|
}
|
|
ea_readbuf(sc, mtod(m, u_char *),
|
|
cp < EA_BUFFER_SIZE ? cp : cp - EA_RX_BUFFER_SIZE,
|
|
len);
|
|
cp += len;
|
|
*mp = m;
|
|
mp = &m->m_next;
|
|
totlen -= len;
|
|
if (cp == epkt)
|
|
cp = addr;
|
|
}
|
|
|
|
return top;
|
|
}
|
|
|
|
/*
|
|
* Process an ioctl request. Mostly boilerplate.
|
|
*/
|
|
static int
|
|
ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
|
{
|
|
struct seeq8005_softc *sc = ifp->if_softc;
|
|
int s, error = 0;
|
|
|
|
s = splnet();
|
|
switch (cmd) {
|
|
|
|
default:
|
|
error = ether_ioctl(ifp, cmd, data);
|
|
if (error == ENETRESET) {
|
|
/*
|
|
* Multicast list has changed; set the hardware filter
|
|
* accordingly.
|
|
*/
|
|
ea_mc_reset(sc);
|
|
error = 0;
|
|
}
|
|
break;
|
|
}
|
|
|
|
splx(s);
|
|
return error;
|
|
}
|
|
|
|
/* Must be called at splnet() */
|
|
static void
|
|
ea_mc_reset(struct seeq8005_softc *sc)
|
|
{
|
|
struct ether_multi *enm;
|
|
struct ether_multistep step;
|
|
int naddr, maxaddrs;
|
|
|
|
naddr = 0;
|
|
maxaddrs = (sc->sc_flags & SEEQ8005_80C04) ? 5 : 0;
|
|
ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm);
|
|
while (enm != NULL) {
|
|
/* Have we got space? */
|
|
if (naddr >= maxaddrs ||
|
|
bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) {
|
|
sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI;
|
|
ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL);
|
|
return;
|
|
}
|
|
ea_set_address(sc, naddr, enm->enm_addrlo);
|
|
sc->sc_config1 |= EA_CFG1_STATION_ADDR0 << naddr;
|
|
naddr++;
|
|
ETHER_NEXT_MULTI(step, enm);
|
|
}
|
|
for (; naddr < maxaddrs; naddr++)
|
|
sc->sc_config1 &= ~(EA_CFG1_STATION_ADDR0 << naddr);
|
|
bus_space_write_2(sc->sc_iot, sc->sc_ioh, EA_8005_CONFIG1,
|
|
sc->sc_config1);
|
|
}
|
|
|
|
/*
|
|
* Device timeout routine.
|
|
*
|
|
* Ok I am not sure exactly how the device timeout should work....
|
|
* Currently what will happens is that that the device timeout is only
|
|
* set when a packet it received. This indicates we are on an active
|
|
* network and thus we should expect more packets. If non arrive in
|
|
* in the timeout period then we reinitialise as we may have jammed.
|
|
* We zero the timeout at this point so that we don't end up with
|
|
* an endless stream of timeouts if the network goes down.
|
|
*/
|
|
|
|
static void
|
|
ea_watchdog(struct ifnet *ifp)
|
|
{
|
|
struct seeq8005_softc *sc = ifp->if_softc;
|
|
|
|
log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
|
|
ifp->if_oerrors++;
|
|
dprintf(("ea_watchdog: "));
|
|
dprintf(("st=%04x\n",
|
|
bus_space_read_2(sc->sc_iot, sc->sc_ioh, EA_8005_STATUS)));
|
|
|
|
/* Kick the interface */
|
|
|
|
ea_init(ifp);
|
|
|
|
/* ifp->if_timer = EA_TIMEOUT;*/
|
|
ifp->if_timer = 0;
|
|
}
|
|
|
|
/* End of if_ea.c */
|