f2973e2fb8
- Free bus_dma resources if attach fails - Add detach and power management code Patch from Masanori Kanaoka <kanaoka@ann.hi-ho.ne.jp> in kern/10156.
316 lines
11 KiB
C
316 lines
11 KiB
C
/* $NetBSD: rtl81x9reg.h,v 1.5 2000/05/19 13:42:29 tsutsui Exp $ */
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/*
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* Copyright (c) 1997, 1998
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp
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*/
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/*
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* RealTek 8129/8139 register offsets
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*/
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#define RTK_IDR0 0x0000 /* ID register 0 (station addr) */
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#define RTK_IDR1 0x0001 /* Must use 32-bit accesses (?) */
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#define RTK_IDR2 0x0002
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#define RTK_IDR3 0x0003
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#define RTK_IDR4 0x0004
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#define RTK_IDR5 0x0005
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/* 0006-0007 reserved */
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#define RTK_MAR0 0x0008 /* Multicast hash table */
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#define RTK_MAR1 0x0009
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#define RTK_MAR2 0x000A
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#define RTK_MAR3 0x000B
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#define RTK_MAR4 0x000C
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#define RTK_MAR5 0x000D
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#define RTK_MAR6 0x000E
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#define RTK_MAR7 0x000F
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#define RTK_TXSTAT0 0x0010 /* status of TX descriptor 0 */
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#define RTK_TXSTAT1 0x0014 /* status of TX descriptor 1 */
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#define RTK_TXSTAT2 0x0018 /* status of TX descriptor 2 */
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#define RTK_TXSTAT3 0x001C /* status of TX descriptor 3 */
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#define RTK_TXADDR0 0x0020 /* address of TX descriptor 0 */
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#define RTK_TXADDR1 0x0024 /* address of TX descriptor 1 */
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#define RTK_TXADDR2 0x0028 /* address of TX descriptor 2 */
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#define RTK_TXADDR3 0x002C /* address of TX descriptor 3 */
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#define RTK_RXADDR 0x0030 /* RX ring start address */
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#define RTK_RX_EARLY_BYTES 0x0034 /* RX early byte count */
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#define RTK_RX_EARLY_STAT 0x0036 /* RX early status */
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#define RTK_COMMAND 0x0037 /* command register */
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#define RTK_CURRXADDR 0x0038 /* current address of packet read */
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#define RTK_CURRXBUF 0x003A /* current RX buffer address */
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#define RTK_IMR 0x003C /* interrupt mask register */
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#define RTK_ISR 0x003E /* interrupt status register */
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#define RTK_TXCFG 0x0040 /* transmit config */
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#define RTK_RXCFG 0x0044 /* receive config */
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#define RTK_TIMERCNT 0x0048 /* timer count register */
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#define RTK_MISSEDPKT 0x004C /* missed packet counter */
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#define RTK_EECMD 0x0050 /* EEPROM command register */
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#define RTK_CFG0 0x0051 /* config register #0 */
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#define RTK_CFG1 0x0052 /* config register #1 */
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/* 0053-0057 reserved */
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#define RTK_MEDIASTAT 0x0058 /* media status register (8139) */
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/* 0059-005A reserved */
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#define RTK_MII 0x005A /* 8129 chip only */
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#define RTK_HALTCLK 0x005B
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#define RTK_MULTIINTR 0x005C /* multiple interrupt */
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#define RTK_PCIREV 0x005E /* PCI revision value */
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/* 005F reserved */
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#define RTK_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
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/* Direct PHY access registers only available on 8139 */
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#define RTK_BMCR 0x0062 /* PHY basic mode control */
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#define RTK_BMSR 0x0064 /* PHY basic mode status */
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#define RTK_ANAR 0x0066 /* PHY autoneg advert */
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#define RTK_LPAR 0x0068 /* PHY link partner ability */
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#define RTK_ANER 0x006A /* PHY autoneg expansion */
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#define RTK_DISCCNT 0x006C /* disconnect counter */
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#define RTK_FALSECAR 0x006E /* false carrier counter */
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#define RTK_NWAYTST 0x0070 /* NWAY test register */
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#define RTK_RX_ER 0x0072 /* RX_ER counter */
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#define RTK_CSCFG 0x0074 /* CS configuration register */
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/*
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* TX config register bits
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*/
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#define RTK_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
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#define RTK_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
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#define RTK_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
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#define RTK_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
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#define RTK_TXCFG_IFG 0x03000000 /* interframe gap */
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#define RTK_TXDMA_16BYTES 0x00000000
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#define RTK_TXDMA_32BYTES 0x00000100
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#define RTK_TXDMA_64BYTES 0x00000200
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#define RTK_TXDMA_128BYTES 0x00000300
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#define RTK_TXDMA_256BYTES 0x00000400
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#define RTK_TXDMA_512BYTES 0x00000500
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#define RTK_TXDMA_1024BYTES 0x00000600
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#define RTK_TXDMA_2048BYTES 0x00000700
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/*
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* Transmit descriptor status register bits.
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*/
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#define RTK_TXSTAT_LENMASK 0x00001FFF
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#define RTK_TXSTAT_OWN 0x00002000
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#define RTK_TXSTAT_TX_UNDERRUN 0x00004000
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#define RTK_TXSTAT_TX_OK 0x00008000
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#define RTK_TXSTAT_EARLY_THRESH 0x003F0000
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#define RTK_TXSTAT_COLLCNT 0x0F000000
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#define RTK_TXSTAT_CARR_HBEAT 0x10000000
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#define RTK_TXSTAT_OUTOFWIN 0x20000000
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#define RTK_TXSTAT_TXABRT 0x40000000
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#define RTK_TXSTAT_CARRLOSS 0x80000000
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/*
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* Interrupt status register bits.
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*/
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#define RTK_ISR_RX_OK 0x0001
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#define RTK_ISR_RX_ERR 0x0002
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#define RTK_ISR_TX_OK 0x0004
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#define RTK_ISR_TX_ERR 0x0008
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#define RTK_ISR_RX_OVERRUN 0x0010
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#define RTK_ISR_PKT_UNDERRUN 0x0020
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#define RTK_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
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#define RTK_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
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#define RTK_ISR_SYSTEM_ERR 0x8000
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#define RTK_INTRS \
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(RTK_ISR_TX_OK|RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \
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RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \
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RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR)
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/*
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* Media status register. (8139 only)
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*/
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#define RTK_MEDIASTAT_RXPAUSE 0x01
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#define RTK_MEDIASTAT_TXPAUSE 0x02
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#define RTK_MEDIASTAT_LINK 0x04
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#define RTK_MEDIASTAT_SPEED10 0x08
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#define RTK_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
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#define RTK_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
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/*
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* Receive config register.
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*/
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#define RTK_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
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#define RTK_RXCFG_RX_INDIV 0x00000002 /* match filter */
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#define RTK_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
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#define RTK_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
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#define RTK_RXCFG_RX_RUNT 0x00000010
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#define RTK_RXCFG_RX_ERRPKT 0x00000020
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#define RTK_RXCFG_WRAP 0x00000080
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#define RTK_RXCFG_MAXDMA 0x00000700
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#define RTK_RXCFG_BUFSZ 0x00001800
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#define RTK_RXCFG_FIFOTHRESH 0x0000E000
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#define RTK_RXCFG_EARLYTHRESH 0x07000000
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#define RTK_RXDMA_16BYTES 0x00000000
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#define RTK_RXDMA_32BYTES 0x00000100
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#define RTK_RXDMA_64BYTES 0x00000200
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#define RTK_RXDMA_128BYTES 0x00000300
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#define RTK_RXDMA_256BYTES 0x00000400
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#define RTK_RXDMA_512BYTES 0x00000500
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#define RTK_RXDMA_1024BYTES 0x00000600
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#define RTK_RXDMA_UNLIMITED 0x00000700
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#define RTK_RXBUF_8 0x00000000
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#define RTK_RXBUF_16 0x00000800
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#define RTK_RXBUF_32 0x00001000
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#define RTK_RXBUF_64 0x00001800
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#define RTK_RXFIFO_16BYTES 0x00000000
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#define RTK_RXFIFO_32BYTES 0x00002000
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#define RTK_RXFIFO_64BYTES 0x00004000
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#define RTK_RXFIFO_128BYTES 0x00006000
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#define RTK_RXFIFO_256BYTES 0x00008000
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#define RTK_RXFIFO_512BYTES 0x0000A000
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#define RTK_RXFIFO_1024BYTES 0x0000C000
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#define RTK_RXFIFO_NOTHRESH 0x0000E000
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/*
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* Bits in RX status header (included with RX'ed packet
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* in ring buffer).
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*/
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#define RTK_RXSTAT_RXOK 0x00000001
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#define RTK_RXSTAT_ALIGNERR 0x00000002
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#define RTK_RXSTAT_CRCERR 0x00000004
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#define RTK_RXSTAT_GIANT 0x00000008
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#define RTK_RXSTAT_RUNT 0x00000010
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#define RTK_RXSTAT_BADSYM 0x00000020
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#define RTK_RXSTAT_BROAD 0x00002000
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#define RTK_RXSTAT_INDIV 0x00004000
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#define RTK_RXSTAT_MULTI 0x00008000
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#define RTK_RXSTAT_LENMASK 0xFFFF0000
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#define RTK_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
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/*
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* Command register.
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*/
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#define RTK_CMD_EMPTY_RXBUF 0x0001
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#define RTK_CMD_TX_ENB 0x0004
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#define RTK_CMD_RX_ENB 0x0008
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#define RTK_CMD_RESET 0x0010
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/*
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* EEPROM control register
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*/
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#define RTK_EE_DATAOUT 0x01 /* Data out */
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#define RTK_EE_DATAIN 0x02 /* Data in */
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#define RTK_EE_CLK 0x04 /* clock */
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#define RTK_EE_SEL 0x08 /* chip select */
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#define RTK_EE_MODE (0x40|0x80)
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#define RTK_EEMODE_OFF 0x00
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#define RTK_EEMODE_AUTOLOAD 0x40
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#define RTK_EEMODE_PROGRAM 0x80
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#define RTK_EEMODE_WRITECFG (0x80|0x40)
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/* 9346/9356 EEPROM commands */
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#define RTK_EEADDR_LEN0 6 /* 9346 */
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#define RTK_EEADDR_LEN1 8 /* 9356 */
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#define RTK_EECMD_LEN 4
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#define RTK_EECMD_WRITE 0x5 /* 0101b */
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#define RTK_EECMD_READ 0x6 /* 0110b */
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#define RTK_EECMD_ERASE 0x7 /* 0111b */
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#define RTK_EE_ID 0x00
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#define RTK_EE_PCI_VID 0x01
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#define RTK_EE_PCI_DID 0x02
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/* Location of station address inside EEPROM */
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#define RTK_EE_EADDR0 0x07
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#define RTK_EE_EADDR1 0x08
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#define RTK_EE_EADDR2 0x09
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/*
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* MII register (8129 only)
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*/
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#define RTK_MII_CLK 0x01
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#define RTK_MII_DATAIN 0x02
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#define RTK_MII_DATAOUT 0x04
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#define RTK_MII_DIR 0x80 /* 0 == input, 1 == output */
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/*
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* Config 0 register
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*/
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#define RTK_CFG0_ROM0 0x01
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#define RTK_CFG0_ROM1 0x02
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#define RTK_CFG0_ROM2 0x04
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#define RTK_CFG0_PL0 0x08
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#define RTK_CFG0_PL1 0x10
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#define RTK_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
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#define RTK_CFG0_PCS 0x40
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#define RTK_CFG0_SCR 0x80
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/*
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* Config 1 register
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*/
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#define RTK_CFG1_PWRDWN 0x01
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#define RTK_CFG1_SLEEP 0x02
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#define RTK_CFG1_IOMAP 0x04
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#define RTK_CFG1_MEMMAP 0x08
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#define RTK_CFG1_RSVD 0x10
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#define RTK_CFG1_DRVLOAD 0x20
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#define RTK_CFG1_LED0 0x40
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#define RTK_CFG1_FULLDUPLEX 0x40 /* 8129 only */
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#define RTK_CFG1_LED1 0x80
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/*
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* The RealTek doesn't use a fragment-based descriptor mechanism.
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* Instead, there are only four register sets, each or which represents
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* one 'descriptor.' Basically, each TX descriptor is just a contiguous
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* packet buffer (32-bit aligned!) and we place the buffer addresses in
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* the registers so the chip knows where they are.
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*
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* We can sort of kludge together the same kind of buffer management
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* used in previous drivers, but we have to do buffer copies almost all
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* the time, so it doesn't really buy us much.
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*
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* For reception, there's just one large buffer where the chip stores
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* all received packets.
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*/
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#define RTK_RX_BUF_SZ RTK_RXBUF_64
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#define RTK_RXBUFLEN (1 << ((RTK_RX_BUF_SZ >> 11) + 13))
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#define RTK_TX_LIST_CNT 4
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#define RTK_TX_EARLYTHRESH ((256 / 32) << 16)
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#define RTK_RX_FIFOTHRESH RTK_RXFIFO_256BYTES
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#define RTK_RX_MAXDMA RTK_RXDMA_256BYTES
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#define RTK_TX_MAXDMA RTK_TXDMA_256BYTES
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#define RTK_RXCFG_CONFIG (RTK_RX_FIFOTHRESH|RTK_RX_MAXDMA|RTK_RX_BUF_SZ)
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#define RTK_TXCFG_CONFIG (RTK_TXCFG_IFG|RTK_TX_MAXDMA)
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