234 lines
5.4 KiB
C
234 lines
5.4 KiB
C
/* $NetBSD: vr41xx.c,v 1.4 2000/01/16 11:14:49 uch Exp $ */
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/*-
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* Copyright (c) 1999 Shin Takemura.
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* All rights reserved.
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*
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* This software is part of the PocketBSD.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the PocketBSD project
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* and its contributors.
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* 4. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <pbsdboot.h>
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extern void vr41xx_asm_code();
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extern void vr41xx_asm_code_end();
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void vr41xx_asm_code_holder __P((void));
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void
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vr41xx_init(SYSTEM_INFO *info)
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{
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/* 1KByte page */
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system_info.si_pagesize = info->dwPageSize;
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/* DRAM Bank 0/1 physical addr range */
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system_info.si_dramstart = 0x80000000;
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system_info.si_drammaxsize = 0x08000000;
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/* Pointer for bootstrap code */
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system_info.si_asmcode = (unsigned char*)vr41xx_asm_code;
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system_info.si_asmcodelen = (unsigned char*)vr41xx_asm_code_end
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- system_info.si_asmcode;
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system_info.si_boot = mips_boot;
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system_info.si_intrvec = 0;
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}
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void
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vr41xx_asm_code_holder()
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{
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/*
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* void
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* startprog(register struct map_s *map)
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* {
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* register unsigned char *addr;
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* register unsigned char *p;
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* register int i;
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*
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* addr = map->base;
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* i = 0;
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* while (p = map->leaf[i / map->leafsize][i % map->leafsize]) {
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* register unsigned char *pe = p + map->pagesize;
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* while (p < pe) {
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* *addr++ = *p++;
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* }
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* i++;
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* }
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* }
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*
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* register assignment:
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* struct map_s *map a0
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* unsigned char *addr a1
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* unsigned char *p a2
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* unsigned char *pe a3
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* int i t0
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*
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* struct map_s {
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* caddr_t entry; +0
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* caddr_t base; +4
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* int pagesize; +8
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* int leafsize; +12
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* int nleaves; +16
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* caddr_t arg0; +20
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* caddr_t arg1; +24
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* caddr_t arg2; +28
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* caddr_t arg3; +32
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* caddr_t *leaf[32]; +36
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*
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*/
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__asm(
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" .set noreorder; "
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" .globl vr41xx_asm_code;"
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"vr41xx_asm_code:"
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" lui a0, 0x0000; "
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" ori a0, 0x0000; "
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/* addr = map->base; */
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"lw a1, 4(a0);"
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/* i = 0; */
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"ori t0, zero, 0;"
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" loop_start:"
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/* while (p = map->leaf[i / map->leafsize][i % map->leafsize]) { */
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/* t1 = map->leafsize */
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"lw t1, 12(a0);"
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/* lo = i / map->leafsize, hi = i % map->leafsize */
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"addu t3, zero, t0;"
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"div t3, t1;"
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/* t2 = map->leaf */
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"addiu t2, a0, 36;"
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/* t3 = i / map->leafsize */
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"nop;"
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"mflo t3;"
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/* t2 = map->leaf[i / map->leafsize] */
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"sll t3, t3, 2;"
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"addu t2, t2, t3;"
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"lw t2, 0(t2);"
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/* t3 = i % map->leafsize */
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"mfhi t3;"
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/* p = map->leaf[i / map->leafsize][i % map->leafsize] */
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"sll t3, t3, 2;"
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"addu t2, t2, t3;"
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"lw a2, 0(t2);"
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/* if (p == NULL) { */
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/* break; */
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/* } */
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"beq a2, zero, loop_end;"
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"nop;"
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/* register unsigned char *pe = p + map->pagesize; */
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"lw t1, 8(a0);"
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"add a3, a2, t1;"
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/* while (p < pe) { */
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"loop_start2:"
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"sltu t1, a2, a3;"
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"beq zero,t1,loop_end2;"
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"nop;"
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/* *addr++ = *p++; */
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"lw t1, 0(a2);"
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"sw t1, 0(a1);"
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"addi a2, a2, 4;"
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"addi a1, a1, 4;"
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/* } */
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"beq zero, zero, loop_start2;"
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"nop;"
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/* i++; */
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"loop_end2:"
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"addi t0, t0, 1;"
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"beq zero, zero, loop_start;"
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"nop;"
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" loop_end:"
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);
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/*
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* flush instruction cache
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*/
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__asm(
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" li t0, 0x80000000;"
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" addu t1, t0, 1024*128;"
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" subu t1, t1, 128;"
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"1:"
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" cache 0, 0(t0);"
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" cache 0, 16(t0);"
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" cache 0, 32(t0);"
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" cache 0, 48(t0);"
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" cache 0, 64(t0);"
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" cache 0, 80(t0);"
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" cache 0, 96(t0);"
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" cache 0, 112(t0);"
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" bne t0, t1, 1b;"
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" addu t0, t0, 128;"
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);
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/*
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* flush data cache
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*/
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__asm(
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" li t0, 0x80000000;"
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" addu t1, t0, 1024*128;"
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" subu t1, t1, 128;"
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"1:"
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" cache 1, 0(t0);"
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" cache 1, 16(t0);"
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" cache 1, 32(t0);"
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" cache 1, 48(t0);"
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" cache 1, 64(t0);"
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" cache 1, 80(t0);"
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" cache 1, 96(t0);"
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" cache 1, 112(t0);"
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" bne t0, t1, 1b;"
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" addu t0, t0, 128;"
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);
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__asm(
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" lw t0, 0(a0);" /* entry addr */
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" lw a1, 24(a0);" /* arg1 */
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" lw a2, 28(a0);" /* arg2 */
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" lw a3, 32(a0);" /* arg3 */
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" lw a0, 20(a0);" /* arg0 */
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" jr t0;"
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" nop;"
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" .globl vr41xx_asm_code_end;"
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"vr41xx_asm_code_end: nop;"
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" .set reorder; "
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);
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}
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