251 lines
14 KiB
C
251 lines
14 KiB
C
#ifndef _POWERPC_SPR_H_
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#define _POWERPC_SPR_H_
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#ifndef _LOCORE
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#define mtspr(reg, val) \
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__asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
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#define mfspr(reg) \
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( { u_int32_t val; \
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__asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
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val; } )
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#endif /* _LOCORE */
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/*
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* Special Purpose Register declarations.
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*
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* The first column in the comments indicates which PowerPC
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* architectures the SPR is valid on - 4 for 4xx series,
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* 6 for 6xx/7xx series and 8 for 8xx and 8xxx series.
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*/
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#define SPR_XER 0x001 /* 468 Fixed Point Exception Register */
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#define SPR_LR 0x008 /* 468 Link Register */
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#define SPR_CTR 0x009 /* 468 Count Register */
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#define SPR_DSISR 0x012 /* .68 DSI exception source */
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#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */
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#define DSISR_NOTFOUND 0x40000000 /* Translation not found */
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#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */
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#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */
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#define DSISR_STORE 0x02000000 /* Store operation */
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#define DSISR_DABR 0x00400000 /* DABR match */
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#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */
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#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */
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#define SPR_DAR 0x013 /* .68 Data Address Register */
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#define SPR_DEC 0x016 /* .68 DECrementer register */
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#define SPR_SDR1 0x019 /* .68 Page table base address register */
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#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */
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#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */
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#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
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#define SPR_SPRG0 0x110 /* 468 SPR General 0 */
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#define SPR_SPRG1 0x111 /* 468 SPR General 1 */
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#define SPR_SPRG2 0x112 /* 468 SPR General 2 */
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#define SPR_SPRG3 0x113 /* 468 SPR General 3 */
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#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */
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#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */
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#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */
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#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */
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#define SPR_EAR 0x11a /* .68 External Access Register */
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#define SPR_TBL 0x11c /* 468 Time Base Lower */
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#define SPR_TBU 0x11d /* 468 Time Base Upper */
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#define SPR_PVR 0x11f /* 468 Processor Version Register */
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#define MPC601 0x0001
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#define MPC603 0x0003
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#define MPC604 0x0004
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#define MPC602 0x0005
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#define MPC603e 0x0006
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#define MPC603ev 0x0007
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#define MPC750 0x0008
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#define MPC604ev 0x0009
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#define MPC7400 0x000c
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#define MPC620 0x0014
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#define MPC860 0x0050
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#define MPC8240 0x0081
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#define MPC7450 0x8000
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#define MPC7410 0x800c
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#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
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#define SPR_IBAT0L 0x211 /* .68 Instruction BAT Reg 0 Lower */
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#define SPR_IBAT1U 0x212 /* .68 Instruction BAT Reg 1 Upper */
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#define SPR_IBAT1L 0x213 /* .68 Instruction BAT Reg 1 Lower */
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#define SPR_IBAT2U 0x214 /* .68 Instruction BAT Reg 2 Upper */
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#define SPR_IBAT2L 0x215 /* .68 Instruction BAT Reg 2 Lower */
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#define SPR_IBAT3U 0x216 /* .68 Instruction BAT Reg 3 Upper */
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#define SPR_IBAT3L 0x217 /* .68 Instruction BAT Reg 3 Lower */
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#define SPR_DBAT0U 0x218 /* .68 Data BAT Reg 0 Upper */
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#define SPR_DBAT0L 0x219 /* .68 Data BAT Reg 0 Lower */
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#define SPR_DBAT1U 0x21a /* .68 Data BAT Reg 1 Upper */
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#define SPR_DBAT1L 0x21b /* .68 Data BAT Reg 1 Lower */
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#define SPR_DBAT2U 0x21c /* .68 Data BAT Reg 2 Upper */
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#define SPR_DBAT2L 0x21d /* .68 Data BAT Reg 2 Lower */
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#define SPR_DBAT3U 0x21e /* .68 Data BAT Reg 3 Upper */
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#define SPR_DBAT3L 0x21f /* .68 Data BAT Reg 3 Lower */
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#define SPI_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */
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#define SPI_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */
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#define SPI_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */
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#define SPI_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */
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#define SPI_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */
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#define SPI_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */
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#define SPI_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */
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#define SPI_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */
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#define SPI_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */
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#define SPI_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */
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#define SPI_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */
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#define SPI_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */
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#define SPI_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */
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#define SPI_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */
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#define SPI_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */
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#define SPI_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */
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#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */
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#define SPR_PID 0x3b1 /* 4.. Process ID */
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#define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */
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#define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */
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#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */
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#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */
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#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */
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#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */
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#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */
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#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */
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#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */
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#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */
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#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */
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#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */
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#define SPR_SIAR 0x3bc /* .6. Sample Instruction Address Register */
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#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */
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#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */
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#define SPR_PMC3 0x3bb /* .6. Performance Counter Register 3 */
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#define SPR_PMC4 0x3bc /* .6. Performance Counter Register 4 */
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#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */
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#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */
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#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */
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#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */
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#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */
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#define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */
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#define ESR_MCI 0x80000000 /* Machine check - instruction */
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#define ESR_PIL 0x08000000 /* Program interrupt - illegal */
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#define ESR_PPR 0x04000000 /* Program interrupt - privileged */
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#define ESR_PTR 0x02000000 /* Program interrupt - trap */
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#define ESR_DST 0x00800000 /* Data storage interrupt - store fault */
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#define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */
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#define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */
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#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */
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#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */
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#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */
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#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */
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#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */
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#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */
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#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */
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#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */
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#define SPR_TSR 0x3d8 /* 4.. Timer Status Register */
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#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
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#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */
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#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */
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#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occured */
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#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */
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#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */
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#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */
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#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
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#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
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#define SPR_TCR 0x3da /* 4.. Timer Control Register */
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#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */
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#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */
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#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */
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#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */
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#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */
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#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */
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#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */
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#define TCR_WRC_CORE 0x10000000 /* Core reset */
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#define TCR_WRC_CHIP 0x20000000 /* Chip reset */
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#define TCR_WRC_SYSTEM 0x30000000 /* System reset */
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#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
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#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
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#define TCR_FP_MASK 0x03000000 /* FIT Period */
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#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */
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#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */
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#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */
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#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */
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#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
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#define TCR_ARE 0x00400000 /* Auto Reload Enable */
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#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */
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#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */
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#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */
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#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */
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#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */
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#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */
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#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */
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#define DBCR0_EDM 0x80000000 /* External Debug Mode */
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#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
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#define DBCR0_RST_MASK 0x30000000 /* ReSeT */
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#define DBCR0_RST_NONE 0x00000000 /* No action */
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#define DBCR0_RST_CORE 0x10000000 /* Core reset */
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#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */
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#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */
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#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */
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#define DBCR0_BT 0x04000000 /* Branch Taken debug event */
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#define DBCR0_EDE 0x02000000 /* Exception Debug Event */
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#define DBCR0_TDE 0x01000000 /* Trap Debug Event */
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#define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */
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#define DBCR0_IA2 0x00400000 /* IAC 2 debug event */
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#define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */
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#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */
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#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */
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#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */
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#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */
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#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */
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#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
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#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
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#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
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#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */
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#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */
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#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */
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#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */
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#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */
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#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */
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#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */
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#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */
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#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */
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#define L2CR_L2E 0x80000000 /* 0: L2 enable */
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#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */
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#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */
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#define L2SIZ_2M 0x00000000
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#define L2SIZ_256K 0x10000000
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#define L2SIZ_512K 0x20000000
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#define L2SIZ_1M 0x30000000
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#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */
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#define L2CLK_DIS 0x00000000 /* disable L2 clock */
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#define L2CLK_10 0x02000000 /* core clock / 1 */
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#define L2CLK_15 0x04000000 /* / 1.5 */
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#define L2CLK_20 0x08000000 /* / 2 */
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#define L2CLK_25 0x0a000000 /* / 2.5 */
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#define L2CLK_30 0x0c000000 /* / 3 */
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#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */
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#define L2RAM_FLOWTHRU_BURST 0x00000000
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#define L2RAM_PIPELINE_BURST 0x01000000
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#define L2RAM_PIPELINE_LATE 0x01800000
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#define L2CR_L2DO 0x00400000 /* 9: L2 data-only.
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Setting this bit disables instruction
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caching. */
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#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */
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#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable).
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Enables automatic operation of the
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L2ZZ (low-power mode) signal. */
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#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */
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#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */
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#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */
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#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */
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#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */
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#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */
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#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */
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/* progress (read only). */
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#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */
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#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */
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#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */
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#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */
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#define SPR_THRM3 0x3fe /* .6. Thermal Management Register */
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#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */
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#define SPR_PIR 0x3ff /* .6. Processor Identification Register */
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/* Time Base Register declarations */
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#define TBR_TBL 0x10c /* 468 Time Base Lower */
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#define TBR_TBU 0x10d /* 468 Time Base Upper */
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#endif /* !_POWERPC_SPR_H_ */
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