117 lines
5.1 KiB
C
117 lines
5.1 KiB
C
/* $NetBSD: makphyreg.h,v 1.6 2014/05/13 02:53:54 christos Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_MII_MAKPHYREG_H_
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#define _DEV_MII_MAKPHYREG_H_
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/*
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* Marvell 88E1000 ``Alaska'' 10/100/1000 PHY registers.
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*/
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#define MII_MAKPHY_PSCR 0x10 /* PHY specific control register */
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#define PSCR_DIS_JABBER (1U << 0) /* disable jabber */
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#define PSCR_POL_REV (1U << 1) /* polarity reversal */
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#define PSCR_SQE_TEST (1U << 2) /* SQE test */
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#define PSCR_MBO (1U << 3) /* must be one */
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#define PSCR_DIS_125CLK (1U << 4) /* 125CLK low */
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#define PSCR_MDI_XOVER_MODE(x) ((x) << 5) /* crossover mode */
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#define PSCR_LOW_10T_THRESH (1U << 7) /* lower 10BASE-T Rx threshold */
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#define PSCR_FORCE_LINK_GOOD (1U << 10) /* force link good */
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#define PSCR_CRS_ON_TX (1U << 11) /* assert CRS on transmit */
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#define PSCR_RX_FIFO(x) ((x) << 12) /* Rx FIFO depth */
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#define PSCR_TX_FIFO(x) ((x) << 14) /* Tx FIFO depth */
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#define XOVER_MODE_MDI 0
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#define XOVER_MODE_MDIX 1
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#define XOVER_MODE_AUTO 2
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#define MII_MAKPHY_PSSR 0x11 /* PHY specific status register */
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#define PSSR_JABBER (1U << 0) /* jabber indication */
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#define PSSR_POLARITY (1U << 1) /* polarity indiciation */
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#define PSSR_MDIX (1U << 6) /* 1 = MIDX, 0 = MDI */
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#define PSSR_CABLE_LENGTH_get(x) (((x) >> 7) & 0x3)
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#define PSSR_LINK (1U << 10) /* link indication */
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#define PSSR_RESOLVED (1U << 11) /* speed and duplex resolved */
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#define PSSR_PAGE_RECEIVED (1U << 12) /* page received */
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#define PSSR_DUPLEX (1U << 13) /* 1 = FDX */
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#define PSSR_SPEED_get(x) (((x) >> 14) & 0x3)
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#define SPEED_10 0
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#define SPEED_100 1
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#define SPEED_1000 2
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#define SPEED_reserved 3
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#define MII_MAKPHY_IE 0x12 /* Interrupt enable */
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#define IE_JABBER (1U << 0) /* jabber indication */
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#define IE_POL_CHANGED (1U << 1) /* polarity changed */
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#define IE_MDI_XOVER_CHANGED (1U << 6) /* MDI/MDIX changed */
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#define IE_FIFO_OVER_UNDER (1U << 7) /* FIFO over/underflow */
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#define IE_FALSE_CARRIER (1U << 8) /* false carrier detected */
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#define IE_SYMBOL_ERROR (1U << 9) /* symbol error occurred */
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#define IE_LINK_CHANGED (1U << 10) /* link status changed */
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#define IE_ANEG_COMPLETE (1U << 11) /* autonegotiation completed */
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#define IE_PAGE_RECEIVED (1U << 12) /* page received */
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#define IE_DUPLEX_CHANGED (1U << 13) /* duplex changed */
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#define IE_SPEED_CHANGED (1U << 14) /* speed changed */
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#define IE_ANEG_ERROR (1U << 15) /* autonegotiation error occurred */
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#define MII_MAKPHY_IS 0x13 /* Interrupt status */
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/* See Interrupt enable bits */
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#define MII_MAKPHY_EPSC 0x14 /* extended PHY specific control */
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#define EPSC_TX_CLK(x) ((x) << 4) /* transmit clock */
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#define EPSC_TBI_RCLK_DIS (1U << 12) /* TBI RCLK disable */
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#define EPSC_TBI_RX_CLK125_EN (1U << 13) /* TBI RX_CLK125 enable */
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#define EPSC_LINK_DOWN_NO_IDLES (1U << 15) /* 1 = lost lock detect */
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#define MII_MAKPHY_REC 0x15 /* receive error counter */
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#define MII_MAKPHY_EADR 0x16 /* extended address register */
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#define MII_MAKPHY_LEDCTRL 0x18 /* LED control */
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#define LEDCTRL_LED_TX (1U << 0) /* 1 = activ/link, 0 = xmit */
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#define LEDCTRL_LED_RX (1U << 1) /* 1 = activ/link, 1 = recv */
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#define LEDCTRL_LED_DUPLEX (1U << 2) /* 1 = duplex, 0 = dup/coll */
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#define LEDCTRL_LED_LINK (1U << 3) /* 1 = spd/link, 0 = link */
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#define LEDCTRL_BLINK_RATE(x) ((x) << 8)
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#define LEDCTRL_PULSE_STRCH(x) ((x) << 12)
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#define LEDCTRL_DISABLE (1U << 15) /* disable LED */
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#define MII_MAKPHY_ESSR 0x1b /* Extended PHY specific status */
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#define ESSR_FIBER_LINK 0x2000
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#define ESSR_GMII_COPPER 0x000f
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#define ESSR_GMII_FIBER 0x0007
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#define ESSR_TBI_COPPER 0x000d
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#define ESSR_TBI_FIBER 0x0005
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#endif /* _DEV_MII_MAKPHYREG_H_ */
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