386 lines
11 KiB
C
386 lines
11 KiB
C
/* $NetBSD: rmixl_iobus.c,v 1.3 2011/07/01 19:01:31 dyoung Exp $ */
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/*-
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* Copyright (c) 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Cliff Neighbors
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* RMI Peripherals IO Bus support
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* - interface to NOR, NAND, PCMCIA Memory controlers, &etc.
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* - manages the 10 Chip Selects
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* - manages the "Flash" interrupts
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* - manages the "Flash" errors
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*/
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/*
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* iobus control registers are accessed as 32 bits.
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* ALEn and CLEn NAND control registers are defined as 8 bits wide
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* but that seems to be a documentation error.
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*
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* iobus data access may be as 1 or 2 or 4 bytes, even if device is 1 byte wide;
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* the controller will sequence the bytes, in big-endian order.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rmixl_iobus.c,v 1.3 2011/07/01 19:01:31 dyoung Exp $");
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#include "locators.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/bus.h>
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#include <mips/rmi/rmixlreg.h>
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#include <mips/rmi/rmixlvar.h>
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#include <mips/rmi/rmixl_intr.h>
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#include <mips/rmi/rmixl_obiovar.h>
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#include <mips/rmi/rmixl_iobusvar.h>
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// #include <mips/rmi/rmixl_gpiovar.h>
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typedef struct {
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bool cs_allocated;
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uint32_t cs_addr; /* base address on the Peripherals I/O Bus */
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uint32_t cs_mask; /* address mask on the Peripherals I/O Bus */
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uint32_t cs_dev_parm;
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} rmixl_iobus_csconfig_t;
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typedef struct rmixl_iobus_softc {
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device_t sc_dev;
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bus_space_tag_t sc_obio_bst; /* for iobus device controler access */
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bus_space_handle_t sc_obio_bsh; /* " " " " " */
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bus_addr_t sc_obio_addr;
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bus_size_t sc_obio_size;
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bus_space_tag_t sc_iobus_bst; /* for iobus access */
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rmixl_iobus_csconfig_t sc_csconfig[RMIXL_FLASH_NCS];
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} rmixl_iobus_softc_t;
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static int rmixl_iobus_match(device_t, cfdata_t, void *);
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static void rmixl_iobus_attach(device_t, device_t, void *);
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static void rmixl_iobus_csconfig_init(struct rmixl_iobus_softc *);
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static int rmixl_iobus_print(void *, const char *);
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static int rmixl_iobus_search(device_t, cfdata_t, const int *, void *);
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#ifdef NOTYET
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static int rmixl_iobus_intr(void *);
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#endif
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#ifdef RMIXL_IOBUS_DEBUG
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rmixl_iobus_softc_t *rmixl_iobus_sc;
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#endif
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CFATTACH_DECL_NEW(rmixl_iobus, sizeof (rmixl_iobus_softc_t),
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rmixl_iobus_match, rmixl_iobus_attach, NULL, NULL);
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int
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rmixl_iobus_match(device_t parent, cfdata_t match, void *aux)
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{
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struct obio_attach_args *obio = aux;
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if (obio->obio_addr == RMIXL_IO_DEV_FLASH)
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return rmixl_probe_4((volatile uint32_t *)
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RMIXL_IOREG_VADDR(obio->obio_addr));
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return 0;
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}
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void
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rmixl_iobus_attach(device_t parent, device_t self, void *aux)
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{
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rmixl_iobus_softc_t *sc = device_private(self);
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struct obio_attach_args *obio = aux;
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struct rmixl_config *rcp = &rmixl_configuration;
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uint64_t r;
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int err;
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#ifdef RMIXL_IOBUS_DEBUG
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rmixl_iobus_sc = sc;
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#endif
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sc->sc_dev = self;
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sc->sc_obio_bst = obio->obio_eb_bst;
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sc->sc_obio_addr = obio->obio_addr;
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sc->sc_obio_size = 0x1000;
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err = bus_space_map(sc->sc_obio_bst, sc->sc_obio_addr,
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sc->sc_obio_size, 0, &sc->sc_obio_bsh);
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if (err != 0) {
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aprint_error_dev(self,
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"bus space map err %d, iobus space\n", err);
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return;
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}
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r = RMIXL_IOREG_READ(RMIXL_SBC_FLASH_BAR);
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KASSERT((r & 1) != 0); /* BAR is enabled */
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rcp->rc_flash_pbase = RMIXL_FLASH_BAR_TO_BA(r);
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rcp->rc_flash_mask = RMIXL_FLASH_BAR_TO_MASK(r);
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aprint_normal("\n");
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aprint_debug_dev(self,
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"Flash BAR pbase %#" PRIx64 " mask %#" PRIx64 "\n",
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rcp->rc_flash_pbase, rcp->rc_flash_mask);
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/* initialize iobus bus space */
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rmixl_iobus_bus_mem_init(&rcp->rc_iobus_memt, rcp);
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sc->sc_iobus_bst = (bus_space_tag_t)&rcp->rc_iobus_memt;
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/* disable all Flsah interupts */
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bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_FLASH_INT_MASK, 0);
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/* write-1-to-clear Flash interrupt status */
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bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_FLASH_INT_STATUS, ~0);
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rmixl_iobus_csconfig_init(sc);
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/* attach any children */
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config_search_ia(rmixl_iobus_search, self, "rmixl_iobus", NULL);
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}
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static void
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rmixl_iobus_csconfig_init(struct rmixl_iobus_softc *sc)
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{
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rmixl_iobus_csconfig_t *cs = &sc->sc_csconfig[0];
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for (int i=0; i < RMIXL_FLASH_NCS; i++) {
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memset(cs, 0, sizeof(rmixl_iobus_csconfig_t));
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cs->cs_addr = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_FLASH_CSBASE_ADDRn(i)) << 16;
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cs->cs_mask = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_FLASH_CSADDR_MASKn(i)) << 16;
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cs->cs_mask |= __BITS(15,0);
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cs->cs_dev_parm = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_FLASH_CSDEV_PARMn(i));
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aprint_debug_dev(sc->sc_dev,
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"CS#%d: addr 0x%08x mask 0x%08x parm 0x%08x\n",
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i, cs->cs_addr, cs->cs_mask, cs->cs_dev_parm);
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cs++;
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}
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}
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static int
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rmixl_iobus_print(void *aux, const char *pnp)
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{
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struct rmixl_iobus_attach_args *ia = aux;
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if (ia->ia_cs != RMIXL_IOBUSCF_CS_DEFAULT)
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aprint_normal(" CS#%d", ia->ia_cs);
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if (ia->ia_iobus_addr != RMIXL_IOBUSCF_ADDR_DEFAULT) {
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aprint_normal(" addr %#" PRIxBUSADDR, ia->ia_iobus_addr);
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if (ia->ia_iobus_size != RMIXL_IOBUSCF_SIZE_DEFAULT)
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aprint_normal("-%#" PRIxBUSSIZE,
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ia->ia_iobus_addr + (ia->ia_iobus_size - 1));
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}
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if (ia->ia_iobus_intr != RMIXL_IOBUSCF_INTR_DEFAULT)
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aprint_normal(" intr %d", ia->ia_iobus_intr);
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return UNCONF;
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}
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static int
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rmixl_iobus_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
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{
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struct rmixl_iobus_softc *sc = device_private(parent);
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struct rmixl_iobus_attach_args ia;
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rmixl_iobus_csconfig_t *cs;
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ia.ia_obio_bst = sc->sc_obio_bst;
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ia.ia_obio_bsh = sc->sc_obio_bsh;
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ia.ia_iobus_bst = sc->sc_iobus_bst;
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ia.ia_iobus_addr = (bus_addr_t)cf->cf_loc[RMIXL_IOBUSCF_ADDR];
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ia.ia_iobus_size = (bus_size_t)cf->cf_loc[RMIXL_IOBUSCF_SIZE];
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ia.ia_iobus_intr = cf->cf_loc[RMIXL_IOBUSCF_INTR];
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ia.ia_cs = cf->cf_loc[RMIXL_IOBUSCF_CS];
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if (ia.ia_cs != RMIXL_IOBUSCF_CS_DEFAULT) {
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/* CS is configured */
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cs = &sc->sc_csconfig[ia.ia_cs];
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/* ensure exclusive use of chip select */
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if (cs->cs_allocated) {
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aprint_error_dev(parent, "CS#%d already allocated\n",
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ia.ia_cs);
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return 0;
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}
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if (ia.ia_iobus_addr != RMIXL_IOBUSCF_ADDR_DEFAULT) {
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if (ia.ia_iobus_addr != cs->cs_addr) {
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/*
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* both CS and addr are configured,
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* ensure they match
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*/
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aprint_error_dev(parent,
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"CS#%d addr 0x%08x mismatch cf_loc "
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"addr 0x%08" PRIxBUSADDR "\n",
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ia.ia_cs, cs->cs_addr, ia.ia_iobus_addr);
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return 0;
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}
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} else {
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/* no addr configured, pull from CS */
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ia.ia_iobus_addr = cs->cs_addr;
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}
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} else {
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/* addr is configured, CS is not; search for matching CS */
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bool found = false;
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cs = &sc->sc_csconfig[0];
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for (int i=0; i < RMIXL_FLASH_NCS; i++) {
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if (cs->cs_allocated)
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continue;
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if (cs->cs_addr == ia.ia_iobus_addr) {
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ia.ia_cs = i;
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found = true;
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break;
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}
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cs++;
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}
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if (! found) {
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aprint_error_dev(parent, "no CS for addr 0x%08"
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PRIxBUSADDR "\n", ia.ia_iobus_addr);
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return 0;
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}
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}
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if (ia.ia_iobus_size != RMIXL_IOBUSCF_SIZE_DEFAULT) {
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/* ensure size fits w/ CS mask */
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if ((ia.ia_iobus_size - 1) > (bus_size_t)cs->cs_mask) {
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aprint_error_dev(parent, "size %#" PRIxBUSSIZE
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" exceeds CS#%d mask 0x%08x\n",
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ia.ia_iobus_size, ia.ia_cs, cs->cs_mask);
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}
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} else {
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/* size not configured, pull from CS */
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ia.ia_iobus_size = (bus_size_t)cs->cs_mask + 1;
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}
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ia.ia_dev_parm = cs->cs_dev_parm;
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if (config_match(parent, cf, &ia) > 0) {
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cs->cs_allocated = true;
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config_attach(parent, cf, &ia, rmixl_iobus_print);
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}
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return 0;
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}
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#ifdef NOTYET
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void
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rmixl_iobus_intr_disestablish(void *uh, void *ih)
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{
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rmixl_iobus_softc_t *sc = uh;
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u_int intr;
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for (intr=0; intr <= RMIXL_UB_INTERRUPT_MAX; intr++) {
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if (ih == &sc->sc_dispatch[intr]) {
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uint32_t r;
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/* disable this interrupt in the usb interface */
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r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_USB_INTERRUPT_ENABLE);
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r &= 1 << intr;
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bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_USB_INTERRUPT_ENABLE, r);
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/* free the dispatch slot */
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sc->sc_dispatch[intr].func = NULL;
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sc->sc_dispatch[intr].arg = NULL;
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break;
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}
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}
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}
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void *
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rmixl_iobus_intr_establish(void *uh, u_int intr, int (func)(void *), void *arg)
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{
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rmixl_iobus_softc_t *sc = uh;
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uint32_t r;
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void *ih = NULL;
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int s;
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s = splusb();
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if (intr > RMIXL_UB_INTERRUPT_MAX) {
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aprint_error_dev(sc->sc_dev, "invalid intr %d\n", intr);
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goto out;
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}
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if (sc->sc_dispatch[intr].func != NULL) {
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aprint_error_dev(sc->sc_dev, "intr %dq busy\n", intr);
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goto out;
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}
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sc->sc_dispatch[intr].func = func;
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sc->sc_dispatch[intr].arg = arg;
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ih = &sc->sc_dispatch[intr];
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/* enable this interrupt in the usb interface */
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r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_USB_INTERRUPT_ENABLE);
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r |= 1 << intr;
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bus_space_write_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_USB_INTERRUPT_ENABLE, r);
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out:
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splx(s);
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return ih;
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}
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static int
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rmixl_iobus_intr(void *arg)
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{
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rmixl_iobus_softc_t *sc = arg;
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uint32_t r;
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int intr;
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int rv = 0;
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r = bus_space_read_4(sc->sc_obio_bst, sc->sc_obio_bsh,
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RMIXL_USB_INTERRUPT_STATUS);
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if (r != 0) {
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for (intr=0; intr <= RMIXL_UB_INTERRUPT_MAX; intr++) {
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uint32_t bit = 1 << intr;
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if ((r & bit) != 0) {
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int (*f)(void *) = sc->sc_dispatch[intr].func;
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void *a = sc->sc_dispatch[intr].arg;
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if (f != NULL) {
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(void)(*f)(a);
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sc->sc_dispatch[intr].count.ev_count++;
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rv = 1;
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}
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}
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}
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}
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return rv;
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}
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#endif /* NOTYET */
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